NXP Semiconductors A3T21H450W23SR6
- Part No.:
- A3T21H450W23SR6
- Manufacturer:
- NXP Semiconductors
- Category:
- Single FETs, MOSFETs
- Package:
- ACP-1230S-4L2S
- Datasheet:
-
A3T21H450W23SR6.pdf
- Description:
- RF MOSFET LDMOS 30V ACP1230S-4
- Quantity:
- Payment:

- Shipping:

Inventory:5,328
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
A3T21H450W23SR6 from NXP Semiconductors is an asymmetrical Doherty RF power LDMOS transistor designed for cellular base station amplifiers operating in the 2110–2200 MHz band. It delivers 87 W average output power at 30 Vdc, achieves 48.9% drain efficiency at 2155 MHz, and maintains –30.2 dBc ACPR under single-carrier W-CDMA with 9.9 dB PAR. Its dual-gate architecture supports carrier-peaking operation in macrocell and massive MIMO active antenna systems.
For engineers reviewing the A3T21H450W23SR6 datasheet, A3T21H450W23SR6 pinout, A3T21H450W23SR6 application, or A3T21H450W23SR6 equivalent, this device requires attention to its 6-pin ACP-1230S-4L2S air-cavity package, gate voltage sequencing (VGSA/Q = 2.2–3.0 Vdc, VGSB = 0.5 Vdc), thermal resistance (RθJC = 0.16 °C/W), and Doherty-specific biasing constraints including mandatory VDDA/VDDB tie-together and prohibition of VDD current through pins 3 and 6.
Technical Context
This device implements a monolithic dual-gate LDMOS structure with physically separate carrier (Side A) and peaking (Side B) transistors in a single die. The carrier side operates at IDQA = 600 mA quiescent drain current with VGS(th) = 1.4–2.3 Vdc, while the peaking side activates above threshold with VGS(th) = 0.8–1.6 Vdc and is biased at VGSB = 0.5 Vdc for Class C behavior. Both sides share common VDD and are internally input/output matched for 50 Ω systems.
Its asymmetrical Doherty architecture enables wide instantaneous bandwidth (90 MHz) with gain flatness ≤0.7 dB and AM/PM distortion ≤–19° across 2110–2200 MHz. Load-pull data confirms optimized P3dB performance up to 501 W (27.0 dBW) and peak drain efficiency of 69.2% on the carrier side at 2110 MHz under pulsed CW conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Range | 2110–2200 MHz - Full-band operation without retuning; supports LTE Band 1 and n1 deployments. |
| Average Output Power | 87 W @ 30 Vdc - Sustained linear output for multi-carrier W-CDMA with 9.9 dB PAR and 0.01% CCDF probability. |
| Drain Efficiency | 48.9% typ. @ 2155 MHz - Enables high-efficiency macrocell PA stages with reduced cooling requirements. |
| ACPR | –30.2 dBc @ ±5 MHz offset - Meets 3GPP ACLR requirements for adjacent channel leakage suppression. |
| Thermal Resistance | RθJC = 0.16 °C/W - Supports high-power density mounting on copper baseplates with minimal junction temperature rise. |
| Gate Threshold Voltage | VGS(th) = 1.4–2.3 Vdc (Side A), 0.8–1.6 Vdc (Side B) - Enables precise Doherty bias point control and digital predistortion compatibility. |
| P3dB Output Power | 501 W (26.9 dBW) typ. - Delivers headroom for transient peaks in OFDMA-based waveforms like LTE and 5G NR. |
Pinout & Package
The A3T21H450W23SR6 uses the ACP-1230S-4L2S air-cavity ceramic package with 6 leads and integral heat slug. Thermal path is optimized via direct case-to-heatsink contact; no thermal pad reflow required. Pins 4 and 5 are DC-coupled and RF-independent; VDD must be supplied externally to pins 1 and 6 only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (RFoutA/VDSA) | Carrier Drain Output | High-current RF output node for carrier amplifier stage; connects to output combiner network. |
| 2 (VBWA) | Carrier Bias Control | DC bias terminal for carrier gate; used for fine-tuning VGSA(Q) during calibration. |
| 3 (RFinA/VGSA) | Carrier Gate Input | RF input and DC gate bias node for carrier transistor; requires external DC blocking if driven by active source. |
| 4 (RFinB/VGSB) | Peaking Gate Input | RF input and DC gate bias node for peaking transistor; tied to 0.5 Vdc reference for Class C activation. |
| 5 (VBWB) | Peaking Bias Control | DC bias terminal for peaking gate; enables dynamic adjustment of peaking turn-on threshold. |
| 6 (RFoutB/VDSB) | Peaking Drain Output | High-current RF output node for peaking amplifier stage; connects to output combiner network. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetrical Doherty Architecture | Enables >15% bandwidth extension vs. symmetrical designs while maintaining >47% efficiency across 2110–2200 MHz. |
| Integrated Input/Output Matching | Eliminates external matching networks for 50 Ω systems, reducing PCB area and insertion loss in base station PA modules. |
| High VSWR Tolerance | Withstands 10:1 load mismatch at 32 Vdc and 400 W pulsed CW without degradation - critical for antenna system fault resilience. |
| Digital Predistortion (DPD) Compatibility | Low AM/PM distortion (≤–19°) and stable gain flatness (0.7 dB over 90 MHz) enable effective DPD linearization in real-time systems. |
| Extended Negative VGS Range | –6.0 Vdc rating allows deep Class C peaking operation and improved back-off efficiency in multi-tone signals. |
Applications
| Macrocell Base Station Transmitter | Active Antenna System (AAS) PA Module |
|---|---|
Use Scenario: High-power RF final stage in 4T4R or 8T8R LTE/n1 macrocell radios operating at 2110–2200 MHz. IC Role / Device Role / Timing Role: Dual-path Doherty power amplifier core delivering 87 W avg. output with DPD support. Use Value: Achieves 48.9% drain efficiency at full output, reducing thermal load and enabling compact heatsink designs in outdoor cabinets. |
Use Scenario: Integrated PA unit within 64T64R massive MIMO active antenna panels requiring wide instantaneous bandwidth. IC Role / Device Role / Timing Role: Asymmetrical Doherty transistor enabling 90 MHz instantaneous bandwidth without frequency-dependent tuning. Use Value: Gain flatness ≤0.7 dB across band ensures consistent EVM and ACLR performance across all sub-bands in wideband 5G NR deployments. |
| Remote Radio Head (RRH) PA Stage | Multi-Band Base Station Combiner PA |
Use Scenario: Outdoor-rated RRH supporting Band 1 + Band 3 carrier aggregation with shared PA architecture. IC Role / Device Role / Timing Role: High-linearity RF power transistor operating in Doherty mode with digital envelope tracking interface. Use Value: Withstands 10:1 VSWR at 400 W pulsed CW, ensuring operational continuity during antenna cable faults or connector corrosion. |
Use Scenario: Final-stage PA in multi-band base station cabinets where 2110–2200 MHz is combined with lower bands via diplexer. IC Role / Device Role / Timing Role: Internally matched LDMOS transistor minimizing inter-stage filtering and insertion loss in combiner paths. Use Value: Eliminates need for external broadband matching, reducing component count and improving group delay consistency across aggregated carriers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF power amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A3T21H450W23SR5 | R5 suffix denotes 50-unit tape-and-reel packaging; identical electrical specs and pinout to A3T21H450W23SR6. | No functional difference; selected for low-volume prototyping or qualification builds requiring smaller reels. | Choose A3T21H450W23SR5 when production volume does not justify 150-unit R6 reels. |
| MRF6VP2450HR6 | 450 W P3dB, 2110–2200 MHz, but non-Doherty single-ended architecture; higher VDD = 32 V, RθJC = 0.22 °C/W. | Suitable for traditional Class AB PA designs without DPD or asymmetrical efficiency optimization. | Select MRF6VP2450HR6 only when Doherty topology is not required and higher peak power is prioritized over back-off efficiency. |
Compared with A3T21H450W23SR6, the R5 variant offers identical RF performance in smaller packaging for validation, while MRF6VP2450HR6 trades Doherty efficiency gains for higher peak power and simpler biasing-making it less suitable for modern wideband, DPD-driven base stations.
Availability
A3T21H450W23SR6 is available at Aetrix Electronics and suitable for macrocell base stations, active antenna systems, remote radio heads, and multi-band combiner PA designs requiring stable component supply and long-term lifecycle support.
Supply support for A3T21H450W23SR6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communications infrastructure markets.
The A3T21H450W23SR6 belongs to NXP's AIRFAST RF Power portfolio, engineered specifically for energy-efficient, wideband cellular infrastructure amplifiers using advanced Doherty architectures and GaN-compatible packaging.
FAQ
What is the maximum continuous drain voltage rating for the A3T21H450W23SR6?
The A3T21H450W23SR6 has a maximum drain-source voltage rating (VDSS) of +65 Vdc and –0.5 Vdc. This rating applies to both carrier and peaking sides under static conditions. Operation beyond these limits risks irreversible gate oxide damage or avalanche breakdown. The device is rated for 32 Vdc operating voltage (VDD), and exceeding this in continuous service reduces MTTF and violates safe operating area constraints defined in the datasheet.
How is the A3T21H450W23SR6 biased for Doherty operation in a typical base station PA?
The A3T21H450W23SR6 requires asymmetric biasing: carrier side (Side A) is biased at VGSA(Q) = 2.2–3.0 Vdc with IDQA = 600 mA, while peaking side (Side B) is biased at VGSB = 0.5 Vdc to achieve Class C turn-on. VDD must be applied jointly to pins 1 and 6; pins 3 and 6 must never supply VDD current. The A3T21H450W23SR6 datasheet specifies strict sequencing-VGSB must be established before VDD to prevent latch-up.
Does the A3T21H450W23SR6 require external input/output matching networks?
No, the A3T21H450W23SR6 is internally matched for 50 Ω systems on both input and output ports across 2110–2200 MHz. This eliminates discrete matching components in standard base station PA layouts. However, the characterization test circuit (Table 6) includes external capacitors and resistors for stability enhancement and harmonic suppression-not for fundamental impedance transformation. The A3T21H450W23SR6 achieves specified gain and efficiency without external matching when mounted per AN1908 reflow guidelines.
What thermal management guidance applies to the A3T21H450W23SR6 in high-power operation?
The A3T21H450W23SR6 has RθJC = 0.16 °C/W and a maximum case temperature (TC) of +150 °C. To maintain TJ ≤ +225 °C at 87 W avg. output, the heatsink must limit thermal resistance to ≤0.85 °C/W (including interface materials). NXP recommends solder-reflow attachment per AN1908 using Sn96.5/Ag3.0/Cu0.5 paste and flatness-controlled copper baseplates. Forced-air cooling is advised above 60 W continuous dissipation.
Can the A3T21H450W23SR6 be used in 5G NR applications?
Yes, the A3T21H450W23SR6 supports 5G NR n1 deployments due to its 2110–2200 MHz coverage, 90 MHz instantaneous bandwidth, and DPD-friendly linearity (ACPR = –30.2 dBc, AM/PM ≤ –19°). Its asymmetrical Doherty architecture delivers >47% efficiency at 6–8 dB power back-off-critical for 5G's variable-envelope waveforms. The A3T21H450W23SR6 has been characterized with W-CDMA and validated for OFDMA signal fidelity, confirming suitability for 5G NR FR1 uplink/downlink PA stages.
A3T21H450W23SR6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- ACP-1230S-4L2S
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Technology:
- LDMOS
- Configuration:
- -
- Frequency:
- 2.11GHz ~ 2.2GHz
- Gain:
- 15.4dB
- Voltage - Test:
- 30 V
- Current Rating (Amps):
- 10µA
- Noise Figure:
- -
- Current - Test:
- 600 mA
- Power - Output:
- 87W
- Voltage - Rated:
- 65 V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Chassis Mount
- Supplier Device Package:
- ACP-1230S-4L2S
A3T21H450W23SR6 FAQ
1.How can I place an order for A3T21H450W23SR6 through Aetrix?
Please submit a Request for Quotation (RFQ) for A3T21H450W23SR6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A3T21H450W23SR6 reliable?
The price and inventory of A3T21H450W23SR6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A3T21H450W23SR6 is usually 5 days.
3.What payment methods are accepted for A3T21H450W23SR6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A3T21H450W23SR6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A3T21H450W23SR6?
A3T21H450W23SR6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A3T21H450W23SR6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A3T21H450W23SR6?
For technical support, including A3T21H450W23SR6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A3T21H450W23SR6 requirements.
6.How does Aetrix verify that A3T21H450W23SR6 is sourced from the original manufacturer or authorized distributors?
All A3T21H450W23SR6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A3T21H450W23SR6 meets industry standards.
7.What is the process for return or replacement of A3T21H450W23SR6?
All A3T21H450W23SR6 units undergo pre-shipment inspection (PSI). If there is an issue with A3T21H450W23SR6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A3T21H450W23SR6 part is unused and in its original packaging.
Return procedure for A3T21H450W23SR6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
A3T21H450W23SR6 Tags

-
3SK294(TE85L,F)
Toshiba Semiconductor and Storage
-
SAV-551+
Mini-Circuits

-
TAV2-501+
Mini-Circuits

-
CE3514M4-C2
CEL

-
AFT05MS004NT1
NXP USA Inc.
-
SAV-541+
Mini-Circuits

-
CE3512K2-C1
CEL

-
AFM907NT1
NXP Semiconductors

-
SKY65050-372LF
Skyworks Solutions Inc.

-
CE3520K3-C1
CEL

-
AFT09MS007NT1
NXP USA Inc.

-
AFT09MS015NT1
NXP USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
