Allegro MicroSystems A4490EESTR-T
- Part No.:
- A4490EESTR-T
- Manufacturer:
- Allegro MicroSystems
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
A4490EESTR-T.pdf
- Description:
- IC REG BUCK ADJ TRPL 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,632
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Product details
Overview
A4490EESTR-T from Allegro MicroSystems is a triple-output synchronous buck switching regulator IC designed for multi-rail power management in compact embedded systems. It delivers three independently controlled DC/DC outputs (1.0 V/1.5 A, 3.3 V/1.5 A, and 5.0 V/1.5 A), operates from 4.5–34 V input, uses fixed 550 kHz multiphase switching, and integrates internal compensation and charge-pump gate drive - enabling use in photo printers and portable industrial controllers.
For engineers reviewing the A4490EESTR-T datasheet, A4490EESTR-T pinout, A4490EESTR-T application, or A4490EESTR-T equivalent, key selection criteria include its 20-pin 4×4 mm QFN-ES package, independent ENBx enable control per channel, PORZ flag with user-configurable delay via CPOR capacitor, and thermal performance validated to –40°C to +85°C ambient.
Technical Context
The A4490EESTR-T implements peak current-mode control with slope compensation across all three buck regulators, sharing a single clock with 120° phase interleaving to reduce input ripple and EMI. Each channel features independent soft-start (1.25 ms typical), programmable output voltage via external resistor dividers, and pulse-by-pulse current limiting with 2 A minimum peak threshold.
Its bias architecture supports dual power configurations: internal startup from VBB (with 4.3 V UVLO) or externally supplied VDD (3.3–5.5 V), which lowers shutdown threshold to 3.5 V and improves runtime during brownout. The integrated charge pump (VCP) sustains gate drive across full duty cycle range, eliminating clamp circuits and enabling operation down to 3.4 V VBB for low-VOUT rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 34 V - supports wide industrial and automotive battery inputs without pre-regulation |
| Switching Frequency | 550 kHz (±70 kHz) - enables use of small 4.7–15 μH inductors and ceramic output capacitors |
| Output Channels | Three independent buck regulators - configurable as 1.0 V/1.5 A, 3.3 V/1.5 A, and 5.0 V/1.5 A |
| Thermal Resistance | RθJA = 37 °C/W on 4-layer JEDEC PCB - defines heatsinking requirement for 125°C max junction temp |
| Operating Temperature | –40°C to +85°C ambient - qualified for industrial and office automation environments |
| Package | 20-contact 4 mm × 4 mm QFN-ES with exposed thermal pad - enables high-power density layout |
| POR Delay Range | 75–155 ms with 470 nF CPOR capacitor - provides configurable system reset timing after rail stabilization |
Pinout & Package
Package: 20-pin, 4 mm × 4 mm, 0.75 mm nominal height QFN-ES with exposed thermal pad (connected to GND via vias).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1, FB2, FB3 | Feedback input per regulator | Resistor-divider node for closed-loop output voltage regulation (0.8 V reference) |
| ENB1, ENB2, ENB3 | Enable input per regulator | Active-high logic control (VIH ≥ 2 V) - allows staggered startup and dynamic rail sequencing |
| LX1, LX2, LX3 | Switch node per regulator | Connects to external inductor and Schottky diode - carries high-frequency pulsed current |
| VBB1, VBB2, VBB3 | Input supply per regulator | Must be externally tied together - supplies energy to respective buck stage |
| VCP, CP1, CP2 | Charge-pump reservoir & terminals | Generates gate-drive voltage above VBB - eliminates need for external high-side drivers |
| PORZ, CPOR | Power-on-reset output & delay adjust | PORZ is open-drain active-low flag; CPOR sets timer via external capacitor (tPOR = 2.131×10⁵ × CPOR) |
| VDD, GND, PGND | Bias supply & ground returns | VDD accepts 3.3–5.5 V external logic supply; GND and PGND must be connected externally |
Key Features
| Feature | Design Value |
|---|---|
| Multiphase interleaved switching | 120° phase shift between channels reduces input capacitor RMS current by ~50% and cuts EMI peaks |
| Independent soft-start per channel | 1.25 ms typical ramp - prevents inrush current and output overshoot during sequential rail enable |
| Integrated charge-pump gate drive | Eliminates external bootstrap components and enables >90% duty cycle operation at low VBB |
| User-configurable POR delay | Adjustable via single external capacitor on CPOR - ensures reliable system reset after all rails stabilize |
| Comprehensive fault protection | Includes overcurrent (pulse-by-pulse), VBB undervoltage warning (3.6 V), and thermal shutdown (165°C) |
Applications
| Photo Printer Power Management | Inkjet Printer Motor & Logic Rails |
|---|---|
Use Scenario: Supplies regulated 1.0 V, 3.3 V, and 5.0 V rails to ASIC, stepper driver, and interface circuitry in compact photo printers. IC Role / Device Role / Timing Role: Triple-output PMIC managing simultaneous power-up sequencing and brownout resilience during battery-powered operation. Use Value: Interleaved switching minimizes input capacitance size and EMI emissions, critical for FCC-compliant portable printer designs. | Use Scenario: Powers printhead driver ICs, motor controllers, and USB/UART interfaces in inkjet printers with variable load profiles. IC Role / Device Role / Timing Role: Independent ENBx control enables staggered activation of high-current motor rails and low-noise logic rails. Use Value: PORZ flag with adjustable delay ensures microcontroller reset only after all three regulated outputs reach ±2.5% regulation tolerance. |
| Industrial Handheld Scanner | Portable Medical Diagnostic Device |
Use Scenario: Delivers stable 3.3 V for CMOS image sensor, 5.0 V for laser diode driver, and 1.0 V for FPGA core in battery-operated scanners. IC Role / Device Role / Timing Role: Charge-pump gate drive maintains regulation down to 3.4 V VBB - extends usable battery life in Li-ion (3.0–4.2 V) applications. Use Value: Internal compensation and fixed frequency simplify loop design - reduces BOM count and layout area in space-constrained handhelds. | Use Scenario: Provides isolated, low-noise power rails for ADC front-end, wireless transceiver, and display controller in portable diagnostics. IC Role / Device Role / Timing Role: Independent feedback paths (FB1/FB2/FB3) allow optimization of each rail's transient response for mixed-signal integrity. Use Value: Thermal pad and 37 °C/W RθJA enable continuous 1.5 A output per channel without forced air - meets Class II medical enclosure thermal limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPQ4436-AEC1 from Monolithic Power Systems | Automotive-grade AEC-Q100, 3.5–36 V input, but only dual-output (not triple); requires external compensation | Targeted for automotive infotainment, not industrial/portable; lacks PORZ flag and CPOR configurability | Select when AEC-Q100 qualification and higher VIN max are required, and third rail can be generated separately |
| TPS543B20 from Texas Instruments | Single-channel 20 A buck with PMBus interface; no native triple-output integration - requires three separate ICs | Used in server/telecom where digital control and telemetry outweigh cost/size penalties of discrete solution | Select when per-rail telemetry, adaptive voltage scaling, or dynamic phase shedding are mandatory |
Compared with MPQ4436-AEC1 and TPS543B20, the A4490EESTR-T uniquely integrates three synchronized, independently enabled buck regulators with analog POR configuration in a single 4×4 mm QFN - reducing board area by >60% versus discrete solutions and avoiding digital interface overhead of PMBus-based alternatives.
Availability
A4490EESTR-T is available at Aetrix Electronics and suitable for photo printers, industrial handheld scanners, portable medical devices, and office automation equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for A4490EESTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based semiconductor company specializing in high-performance power ICs and magnetic sensors, headquartered in Manchester, NH.
The A4490 product line is engineered for multi-rail power conversion in space-constrained, thermally demanding applications such as printers, portable instrumentation, and industrial controls - emphasizing integration, reliability, and ease of analog design.
FAQ
What is the maximum output current per channel for the A4490EESTR-T?
The A4490EESTR-T supports up to 1.5 A continuous output current per channel (REG1, REG2, REG3) under recommended operating conditions (TA ≤ 85°C, proper PCB thermal design). Peak current limit is 2 A minimum at 90% duty cycle, increasing to ~3.75 A at 30% duty cycle per Figure 3 in the datasheet. Derating is required above 85°C ambient or with inadequate copper pour.
Does the A4490EESTR-T require external compensation components?
No, the A4490EESTR-T features internal compensation for all three buck regulators, eliminating the need for external Type-II or Type-III compensation networks. This simplifies design, reduces BOM count, and improves consistency across production units - confirmed in the "Internal compensation" feature bullet and Functional Block Diagram on page 3 of the datasheet.
How is the power-on-reset (POR) delay configured on the A4490EESTR-T?
The POR delay for the A4490EESTR-T is set by an external capacitor connected to the CPOR pin. Using Equation 1 (tPOR = 2.131 × 10⁵ × CPOR), a 470 nF capacitor yields 75–155 ms typical delay. The capacitor must be placed adjacent to CPOR with a short GND trace to minimize leakage; ceramic X5R/X7R types are specified in the datasheet for stability.
Can the A4490EESTR-T operate with only two of its three regulators enabled?
Yes, the A4490EESTR-T supports partial enablement: ENB1, ENB2, and ENB3 are independent logic inputs, so any combination (e.g., only REG1 and REG2) can be activated. The PORZ flag asserts only after all *enabled* regulators reach 85% of their target FB voltage - disabled channels have no effect on PORZ timing or functionality.
What thermal pad connection is required for the A4490EESTR-T QFN-ES package?
The exposed thermal pad on the A4490EESTR-T QFN-ES package must be soldered to the PCB's GND plane using ≥4 thermal vias (0.3 mm diameter, filled or capped). Per the Terminal List Table footnote [3], this connection is mandatory for achieving the specified RθJA of 37 °C/W and preventing junction temperature exceedance above 125°C under full load.
A4490EESTR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 3
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 34V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 30.6V
- Current - Output:
- -
- Frequency - Switching:
- 550kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN-EP (4x4)
A4490EESTR-T FAQ
1.How can I place an order for A4490EESTR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A4490EESTR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A4490EESTR-T reliable?
The price and inventory of A4490EESTR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A4490EESTR-T is usually 5 days.
3.What payment methods are accepted for A4490EESTR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A4490EESTR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A4490EESTR-T?
A4490EESTR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A4490EESTR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A4490EESTR-T?
For technical support, including A4490EESTR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A4490EESTR-T requirements.
6.How does Aetrix verify that A4490EESTR-T is sourced from the original manufacturer or authorized distributors?
All A4490EESTR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A4490EESTR-T meets industry standards.
7.What is the process for return or replacement of A4490EESTR-T?
All A4490EESTR-T units undergo pre-shipment inspection (PSI). If there is an issue with A4490EESTR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A4490EESTR-T part is unused and in its original packaging.
Return procedure for A4490EESTR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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