Allegro MicroSystems A4942GESTR-T
- Part No.:
- A4942GESTR-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
A4942GESTR-T.pdf
- Description:
- IC MOTOR DRIVER 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:8,679
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Product details
Overview
A4942GESTR-T from Allegro MicroSystems is a three-phase sensorless BLDC fan driver IC with integrated BEMF sensing, closed-loop speed control, PWM speed input (1–50 kHz), FG tachometer output, and overcurrent protection. It operates from 7 to 18 V, delivers up to 1 A phase current, and targets high-reliability 12 V cooling fans in server, telecom, and industrial power supplies.
For engineers reviewing the A4942GESTR-T datasheet, A4942GESTR-T pinout, A4942GESTR-T application, or A4942GESTR-T equivalent, key selection considerations include its sensorless commutation architecture, adjustable min/max speed via external resistors, soft-start current limiting, thermal performance in the 4 mm × 4 mm QFN-20 package, and FG output compatibility with standard fan monitoring circuits.
Technical Context
The A4942GESTR-T implements back-EMF zero-crossing detection for rotor position estimation without Hall sensors, enabling cost-effective and reliable fan operation. Its closed-loop speed regulation uses an internal PI controller that compares FG feedback against PWM duty-cycle demand to adjust drive timing dynamically.
Integrated current limiting employs internal sense FETs with user-adjustable threshold via external resistor, eliminating discrete sense resistors. Soft switching reduces audible noise by controlling slew rate during commutation transitions, while lock detection triggers automatic shutdown on stalled motor conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 7–18 V DC: supports standard 12 V fan rails with margin for ripple and drop. |
| Phase Current Limit | Adjustable up to 1 A: sets peak winding current via external resistor; avoids external sense R. |
| PWM Input Frequency | 1–50 kHz: compatible with common microcontroller PWM outputs and fan speed controllers. |
| FG Output | Open-drain, 2-pulse/rev: provides tachometer signal directly usable by system monitoring ICs. |
| Operating Temp | −40 °C to +105 °C: qualified for industrial and telecom chassis environments. |
| Package | 20-pin QFN, 4 mm × 4 mm, exposed pad: enables >2 W power dissipation with proper PCB copper area. |
Pinout & Package
The A4942GESTR-T is housed in a 20-contact, 4 mm × 4 mm QFN package with exposed thermal pad (ES suffix). Pin numbering follows standard QFN convention, pin 1 marked by dot or chamfered corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Power supply input | 7–18 V main supply; requires local 1 µF ceramic bypass capacitor. |
| GND | Ground reference | Common return for power, logic, and thermal pad; must connect to large PCB ground plane. |
| OUTA/OUTB/OUTC | High-side/low-side gate drivers | Three half-bridge outputs driving external N-channel MOSFETs (not integrated). |
| PHASEA/PHASEB/PHASEC | BEMF sensing inputs | Monitor motor winding voltages for sensorless commutation; require RC filtering per datasheet. |
| PWM | Speed command input | Active-low PWM input; duty cycle sets target speed within min/max bounds set by RMIN/RMAX. |
| FG | Fan tachometer output | Open-drain pulse output (2 pulses per revolution); pulls low for ~1 µs per pulse. |
| EN | Enable control | Active-high logic input; disables all outputs and enters ultra-low quiescent current mode. |
| FAULT | Diagnostic output | Open-drain flag indicating overcurrent, lock, or thermal shutdown; active-low assertion. |
Key Features
| Feature | Design Value |
|---|---|
| Sensorless BEMF commutation | Eliminates Hall sensors and associated wiring, reducing system BOM count and board space by ≥3 components. |
| Closed-loop speed regulation | Maintains ±5% speed accuracy across line/load/temperature with no firmware or external controller required. |
| Adjustable soft-start current limit | Reduces inrush current surge by ramping phase current limit over 10–100 ms, easing power supply stress. |
| FG tachometer output | Provides standardized 2-pulse/rev signal compatible with BMC, IPMI, and legacy fan monitoring circuits. |
| Lock detection & auto-shutdown | Halts drive and asserts FAULT within 50 ms of stall detection, preventing MOSFET overheating and system damage. |
Applications
| Server CPU Cooling Fans | Telecom Power Shelf Fans |
|---|---|
Use Scenario: Forced-air cooling of multi-core CPUs and VRMs in 1U/2U rack servers requiring precise thermal management and health telemetry. IC Role / Device Role / Timing Role: Sensorless BLDC driver managing fan speed via IPMI PWM commands and reporting RPM via FG output to BMC. Use Value: Enables fan speed stabilization under dynamic load, reduces acoustic noise via soft switching, and supports predictive maintenance through FAULT flag logging. | Use Scenario: Redundant cooling in -48 V telecom rectifier shelves where reliability and thermal resilience are critical. IC Role / Device Role / Timing Role: Primary fan controller interfacing with shelf supervisor IC via PWM/FG, operating continuously at −40 °C to +70 °C ambient. Use Value: Delivers lock protection and overcurrent shutdown without external circuitry, extending mean time between failures in unattended deployments. |
| Industrial PLC Enclosure Fans | Medical Imaging Power Supply Fans |
Use Scenario: Convection-assisted cooling of programmable logic controllers mounted in hot, dusty factory enclosures. IC Role / Device Role / Timing Role: Standalone fan speed regulator using analog-set min/max speeds and PWM override, with fault signaling to HMI. Use Value: Maintains consistent airflow despite voltage sag or dust accumulation on blades, thanks to closed-loop speed correction and BEMF-based commutation robustness. | Use Scenario: Cooling high-efficiency switch-mode power supplies inside MRI and CT scanner cabinets where EMI and noise are tightly constrained. IC Role / Device Role / Timing Role: Low-noise BLDC driver with soft-switching and filtered BEMF sensing to minimize conducted/radiated emissions. Use Value: Meets IEC 60601-1 EMI limits without added ferrites or shielding, while providing FG-based thermal derating feedback to system controller. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar three-phase sensorless fan driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP6532GQ-Z | Integrated MOSFETs (30 V, 1.5 A); no external FETs required. Lacks FG output and lock detection. | Better for space-constrained designs with lower current (<1 A) fans; unsuitable where tach feedback or stall protection is mandatory. | Select MP6532GQ-Z only if board area is critical and FG/lock features are handled externally. |
| DRV10983ZRTVT | On-chip MOSFETs (22 V, 1.2 A); includes FG output and stall protection but uses different BEMF algorithm and requires different RC tuning. | Valid for 12 V fans with tighter speed accuracy (±2%) but demands revalidation of loop stability and startup behavior. | Choose DRV10983ZRTVT when higher speed precision is needed and redesign of BEMF filter network is acceptable. |
Compared with MP6532GQ-Z and DRV10983ZRTVT, the A4942GESTR-T uniquely balances external FET flexibility, integrated FG/FAULT diagnostics, and proven BEMF stability across wide temperature and voltage ranges-making it optimal for high-availability fan systems where serviceability and failure visibility matter.
Availability
A4942GESTR-T is available at Aetrix Electronics and suitable for server cooling, telecom power shelf ventilation, and industrial PLC enclosure fans requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for A4942GESTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer of high-performance magnetic sensing and power ICs, specializing in motion control, motor drivers, and precision current sensors.
The A4942GESTR-T belongs to Allegro's brushless DC motor driver product line, engineered specifically for cost-sensitive, high-reliability cooling applications where sensorless operation, diagnostic visibility, and thermal robustness are essential.
FAQ
Does the A4942GESTR-T integrate power MOSFETs, or does it require external FETs?
The A4942GESTR-T is a gate driver IC and does not integrate power MOSFETs. It drives external N-channel MOSFETs in a three-phase half-bridge configuration. This architecture allows designers to select FETs optimized for voltage, current, and thermal requirements-giving full control over RDS(on), switching losses, and layout. The A4942GESTR-T provides matched drive strength and dead-time control for clean commutation.
What is the function of the PHASEA, PHASEB, and PHASEC pins on the A4942GESTR-T?
The PHASEA, PHASEB, and PHASEC pins on the A4942GESTR-T are dedicated BEMF sensing inputs that monitor motor winding voltages during commutation. Each connects to the center tap of its respective phase winding (via RC filter networks specified in the datasheet) to detect zero-crossing events. These signals enable the A4942GESTR-T's sensorless algorithm to determine rotor position and sequence gate drive without Hall sensors.
Can the A4942GESTR-T operate with a 5 V PWM input signal from a microcontroller?
Yes, the A4942GESTR-T PWM input is CMOS-compatible and accepts 0–5 V logic levels. It interprets duty cycle-not voltage amplitude-as the speed command. A 5 V microcontroller GPIO can directly drive the PWM pin, provided the signal meets minimum pulse width (≥1 µs) and frequency (1–50 kHz) requirements. No level-shifting circuitry is needed for standard 5 V MCU interfaces.
How does the A4942GESTR-T implement closed-loop speed control without an external microcontroller?
The A4942GESTR-T embeds a dedicated analog PI controller that compares the FG tachometer frequency against the target speed derived from the PWM duty cycle and external RMIN/RMAX resistors. It adjusts drive timing in real time to maintain speed within ±5% across load and temperature variations-requiring no firmware, external processor, or digital interface. This autonomous regulation is core to the A4942GESTR-T's value in standalone fan modules.
Is the exposed thermal pad on the A4942GESTR-T package required to be soldered to the PCB ground plane?
Yes, the exposed thermal pad on the A4942GESTR-T QFN package must be soldered to a solid PCB copper area connected to GND. This connection serves dual purposes: thermal dissipation (critical for >0.5 A continuous operation) and electrical grounding of the internal power stage. Allegro specifies minimum pad size (≥25 mm²) and solder stencil design (8–10 windows) in the datasheet to ensure reliable thermal performance and mechanical attachment of the A4942GESTR-T.
A4942GESTR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushless DC (BLDC)
- Function:
- Driver - Fully Integrated, Control and Power Stage
- Output Configuration:
- Half Bridge (3)
- Interface:
- PWM
- Technology:
- Power MOSFET
- Step Resolution:
- -
- Applications:
- Fan Motor Driver
- Current - Output:
- -
- Voltage - Supply:
- -
- Voltage - Load:
- -
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN-EP (4x4)
A4942GESTR-T FAQ
1.How can I place an order for A4942GESTR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A4942GESTR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A4942GESTR-T reliable?
The price and inventory of A4942GESTR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A4942GESTR-T is usually 5 days.
3.What payment methods are accepted for A4942GESTR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A4942GESTR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A4942GESTR-T?
A4942GESTR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A4942GESTR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A4942GESTR-T?
For technical support, including A4942GESTR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A4942GESTR-T requirements.
6.How does Aetrix verify that A4942GESTR-T is sourced from the original manufacturer or authorized distributors?
All A4942GESTR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A4942GESTR-T meets industry standards.
7.What is the process for return or replacement of A4942GESTR-T?
All A4942GESTR-T units undergo pre-shipment inspection (PSI). If there is an issue with A4942GESTR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A4942GESTR-T part is unused and in its original packaging.
Return procedure for A4942GESTR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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