Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Interface > Modems - ICs and Modules

onsemi A5191HRTPG-XTP

Name: A5191HRTPG-XTP
Brand: onsemi
SKU: A5191HRTPG-XTP
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: A5191HRTPG-XTP

Manufacturer:: onsemi

Category:: Modems - ICs and Modules

Package:: 28-LCC (J-Lead)

Datasheet:: A5191HRTPG-XTP.pdf

Description:: IC HART MODEM CMOS 28PLCC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,037

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

A5191HRTPG-XTP from onsemi is a single-chip, half-duplex HART physical layer modem IC for field instrument and master applications. It implements Bell 202-compliant 1200 bps FSK modulation/demodulation at 1200 Hz and 2200 Hz, operates from 3.0 V to 5.5 V, supports industrial temperature range (−40 °C to +85 °C), and requires a 460.8 kHz ceramic resonator or external clock.

For engineers reviewing the A5191HRTPG-XTP datasheet, pinout, applications, or equivalent options, this page delivers verified technical context, package-specific pin mapping, real-world HART loop interface design values, and validated alternative options for 4–20 mA loop-powered transmitters and HART multiplexers.

Technical Context

The A5191HRTPG-XTP integrates a numeric-controlled oscillator (NCO) with phase-continuous FSK generation, trapezoidal waveform shaping (1860 V/s slew at mark, 3300 V/s at space), and a three-pole high-pass receive filter. Its carrier detect circuit asserts CD after four consecutive valid cycles of RxA input exceeding 100 mV_p-p, referenced to CDREF = AREF − 80 mV.

Digital logic resets via active-low RESETB (minimum 10 ns low after VDD ≥ 2.5 V); half-duplex operation is controlled by RTSB - low enables transmit (TxA active), high enables receive (RxD/CD active). The internal bias current (2.5 µA) is set by RBIAS connected to CBIAS and referenced to AREF.

Key Specifications

Parameter	Value and Actual Design Meaning
Modulation Scheme	Phase-continuous FSK per Bell 202: 1200 Hz (mark), 2200 Hz (space)
Data Rate	1200 bps - matches HART protocol timing for UART-style 11-bit frames (1 start, 8 data, 1 odd parity, 1 stop)
Supply Voltage	3.0 V to 5.5 V - supports direct interface with 3.3 V or 5 V microcontrollers without level shifters
Operating Temperature	−40 °C to +85 °C - qualified for industrial field instrumentation in harsh environments
Clock Requirement	460.8 kHz ±1% - sourced from external ceramic resonator (XIN/XOUT) or precision clock
Carrier Detect Threshold	Nominal 100 mV_p-p - set by CDREF = AREF − 80 mV; activates CD after 4 consecutive valid cycles
Demodulator Jitter	12% of one bit - measured under spec-compliant input conditions (1200/2200 Hz ± tolerance, 460.8 kHz clock)

Pinout & Package

Package: 28-pin PLCC (Case 776AA), Pb-free, RoHS compliant. Body dimensions: 11.43 mm × 11.43 mm × 3.56 mm (max height).

Pin/Terminal	Circuit Role	Design Meaning
1, 5, 7–9, 14, 25, 28	Factory test pins	Must be tied to VSS per datasheet; unused in normal operation
6, 23	RESETB, RTSB	Active-low digital controls: RESETB holds logic in reset; RTSB selects transmit (low) vs. receive (high) mode
10, 26	TxA, RxD	Analog FSK output (trapezoidal, 0.25–0.75 V) and digital demodulated output (NRZ logic levels)
11–13, 15, 16, 17–18, 19–20, 21–22, 24, 27	AREF, CDREF, CBIAS, VDDA, RxA, RxAF, RxAFI, XOUT, XIN, VSS, VDD, TxD, CD	Reference voltage inputs (AREF/CDREF), analog bias (CBIAS), dual-supply rails (VDD/VDDA, VSS), signal I/O (RxA/RxAF/RxAFI/TxD), oscillator interface (XIN/XOUT), and carrier detect flag (CD)

Key Features

Feature	Design Value
Integrated HART Physical Layer	Fully complies with HART Foundation specifications - no external modulator/demodulator ICs or discrete filters required
Low-Power Half-Duplex Operation	Receive circuits disabled during transmit and vice versa - reduces dynamic current to ≤330 µA (typ) at 3.3 V, enabling intrinsic safety compliance
Self-Contained Oscillator Interface	Accepts 460.8 kHz ceramic resonator directly on XIN/XOUT - eliminates need for external crystal driver or clock generator
Programmable Carrier Detect Sensitivity	CDREF pin allows precise setting of 80–120 mV_p-p detection threshold via AREF offset - ensures reliable operation across varying loop impedances
Robust Analog Front-End	Three-pole high-pass receive filter (RxAF) + comparator (RxAFI) rejects out-of-band noise while preserving HART signal integrity in 4–20 mA loops

Applications

HART Multiplexer Interface	4–20 mA Loop-Powered Transmitter
Use Scenario: Centralized polling of multiple field devices over shared HART-enabled 4–20 mA wiring. IC Role / Device Role / Timing Role: A5191HRTPG-XTP acts as the physical layer modem, converting UART data from host MCU to FSK signals injected into the loop and extracting received FSK back to UART. Use Value: Enables multi-drop communication without modifying existing 4–20 mA infrastructure; supports up to 15 slaves per loop per HART spec.	Use Scenario: Smart sensor transmitter (e.g., pressure, temperature) powered solely by 4–20 mA loop with bidirectional digital configuration and diagnostics. IC Role / Device Role / Timing Role: A5191HRTPG-XTP provides HART modulation/demodulation while operating within strict loop power budget (<4 mA quiescent + dynamic). Use Value: Meets intrinsic safety requirements (low IDD ≤330 µA typ at 3.3 V); eliminates need for auxiliary power supply in field devices.
HART Modem Interface Board	Field Instrument Master Device
Use Scenario: Retrofitting legacy analog instruments with HART capability using an add-on interface board. IC Role / Device Role / Timing Role: A5191HRTPG-XTP serves as standalone modem, interfacing between instrument's analog front-end and host controller's UART. Use Value: Requires only 4 passive components (resonator + bias resistor + two decoupling caps); simplifies certification for hazardous area use.	Use Scenario: Handheld or PC-based HART communicator used for device commissioning, calibration, and diagnostics in plant maintenance. IC Role / Device Role / Timing Role: A5191HRTPG-XTP implements full HART physical layer in portable equipment, handling both master-initiated and slave-responses. Use Value: Supports full HART command set (universal, common practice, device-specific) with guaranteed timing compliance due to integrated NCO and jitter control.

HART Multiplexer Interface

4–20 mA Loop-Powered Transmitter

Use Scenario: Centralized polling of multiple field devices over shared HART-enabled 4–20 mA wiring.

IC Role / Device Role / Timing Role: A5191HRTPG-XTP acts as the physical layer modem, converting UART data from host MCU to FSK signals injected into the loop and extracting received FSK back to UART.

Use Value: Enables multi-drop communication without modifying existing 4–20 mA infrastructure; supports up to 15 slaves per loop per HART spec.

Use Scenario: Smart sensor transmitter (e.g., pressure, temperature) powered solely by 4–20 mA loop with bidirectional digital configuration and diagnostics.

IC Role / Device Role / Timing Role: A5191HRTPG-XTP provides HART modulation/demodulation while operating within strict loop power budget (<4 mA quiescent + dynamic).

Use Value: Meets intrinsic safety requirements (low IDD ≤330 µA typ at 3.3 V); eliminates need for auxiliary power supply in field devices.

HART Modem Interface Board

Field Instrument Master Device

Use Scenario: Retrofitting legacy analog instruments with HART capability using an add-on interface board.

IC Role / Device Role / Timing Role: A5191HRTPG-XTP serves as standalone modem, interfacing between instrument's analog front-end and host controller's UART.

Use Value: Requires only 4 passive components (resonator + bias resistor + two decoupling caps); simplifies certification for hazardous area use.

Use Scenario: Handheld or PC-based HART communicator used for device commissioning, calibration, and diagnostics in plant maintenance.

IC Role / Device Role / Timing Role: A5191HRTPG-XTP implements full HART physical layer in portable equipment, handling both master-initiated and slave-responses.

Use Value: Supports full HART command set (universal, common practice, device-specific) with guaranteed timing compliance due to integrated NCO and jitter control.

Equivalent & Alternatives

The following parts are listed as comparable options for similar HART modem applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD5700-1ACPZ-RL7	Integrated 4–20 mA DAC + HART modem in single package; requires external crystal; higher integration but larger footprint (32-pin LFCSP)	Targeted at loop-powered transmitters needing both analog output and HART comms - not a drop-in replacement for standalone modem use	Select when combining DAC and modem saves board space and simplifies BOM; verify thermal dissipation in sealed enclosures
TI AMIS-42700	Isolated HART modem with integrated galvanic isolation; 5 V only supply; no internal oscillator - requires external 460.8 kHz clock	Designed for systems requiring reinforced isolation between loop side and MCU side - adds safety margin but increases component count	Choose when isolation is mandated by system architecture or safety standards (IEC 61000-4-x, UL 61010); avoid if cost or layout area is constrained

Compared with AD5700-1ACPZ-RL7 and AMIS-42700, the A5191HRTPG-XTP offers lowest system-level BOM count for non-isolated, standalone HART modem designs - requiring only resonator, bias resistor, and decoupling capacitors - while maintaining full HART spec compliance and industrial temperature operation.

Availability

A5191HRTPG-XTP is available at Aetrix Electronics and suitable for HART multiplexers, 4–20 mA loop-powered transmitters, and field instrument master devices requiring stable component supply despite its discontinued status.

Supply support for A5191HRTPG-XTP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, high-performance silicon solutions for automotive, industrial, cloud, medical, and IoT applications.

The A5191HRTPG-XTP belongs to onsemi's industrial communications product line, engineered specifically for robust, low-power HART physical layer implementation in process automation field devices.

FAQ

What is the function of the CBIAS pin on the A5191HRTPG-XTP?

The CBIAS pin on the A5191HRTPG-XTP outputs a 2.5 µA bias current used to set operating points for internal analog blocks including the Rx HP filter and comparators. It must be connected to VSS through an external resistor (RBIAS), calculated as RBIAS = AREF / 2.5 µA - typically 500 kΩ when AREF = 1.235 V. This ensures accurate gain, filtering, and carrier detect thresholds across temperature and supply variations in the A5191HRTPG-XTP.

Does the A5191HRTPG-XTP support both internal and external clock sources?

Yes, the A5191HRTPG-XTP supports both clocking methods: an internal oscillator driven by a 460.8 kHz parallel-mode ceramic resonator connected between XIN and XOUT, or an external 460.8 kHz clock applied to XOUT with XIN grounded. Using an external clock reduces IDD by ~25% versus internal resonator operation, which is critical for ultra-low-power intrinsically safe designs using the A5191HRTPG-XTP.

How does the carrier detect (CD) output behave on the A5191HRTPG-XTP?

The CD output on the A5191HRTPG-XTP goes high when a valid HART signal (>100 mV_p-p) is detected on RxA for four consecutive cycles - corresponding to ~3.33 ms at 1200 Hz or ~1.82 ms at 2200 Hz. CD remains asserted only while RTSB is high (receive mode) and new valid cycles arrive within 2.5 ms. This behavior prevents false triggering from noise and ensures RxD output is gated by CD, as required by HART specification - a core functional guarantee of the A5191HRTPG-XTP.

Can the A5191HRTPG-XTP operate from a 3.3 V supply in a 4–20 mA loop-powered system?

Yes, the A5191HRTPG-XTP is fully specified for 3.0 V to 5.5 V operation and draws ≤330 µA typical supply current at 3.3 V (IDDA), making it suitable for 4–20 mA loop-powered transmitters. Its 3.3 V compatibility eliminates level-shifting needs with common 3.3 V microcontrollers, and its low IDD ensures sufficient headroom within the 3.5 mA typical allocation for digital circuitry in loop-powered devices - a key enabler for compact, certified field instruments using the A5191HRTPG-XTP.

What package type is used by the A5191HRTPG-XTP?

The A5191HRTPG-XTP uses a 28-pin plastic leaded chip carrier (PLCC) package, case number 776AA, with Pb-free (RoHS-compliant) finish. Its dimensions are 11.43 mm × 11.43 mm × 3.56 mm max height, and it features gull-wing leads compatible with standard surface-mount reflow processes. This PLCC variant is distinct from the QFN and LQFP versions (A5191HRTNG-XTP and A5191HRTLG-XTP) - the A5191HRTPG-XTP is the only PLCC option in the family.

A5191HRTPG-XTP Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: -

Package/Case:: 28-LCC (J-Lead)

Packaging:: Tape & Reel (TR)

Product Status:: Last Time Buy

Data Format:: HART

Baud Rates:: 1.2k

Voltage - Supply:: 3V ~ 5V

Mounting Type:: Surface Mount

Supplier Device Package:: 28-PLCC (11.51x11.51)

A5191HRTPG-XTP FAQ

1.How can I place an order for A5191HRTPG-XTP through Aetrix?

Please submit a Request for Quotation (RFQ) for A5191HRTPG-XTP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for A5191HRTPG-XTP reliable?

The price and inventory of A5191HRTPG-XTP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A5191HRTPG-XTP is usually 5 days.

3.What payment methods are accepted for A5191HRTPG-XTP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A5191HRTPG-XTP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for A5191HRTPG-XTP?

A5191HRTPG-XTP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your A5191HRTPG-XTP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for A5191HRTPG-XTP?

For technical support, including A5191HRTPG-XTP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A5191HRTPG-XTP requirements.

6.How does Aetrix verify that A5191HRTPG-XTP is sourced from the original manufacturer or authorized distributors?

All A5191HRTPG-XTP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A5191HRTPG-XTP meets industry standards.

7.What is the process for return or replacement of A5191HRTPG-XTP?

All A5191HRTPG-XTP units undergo pre-shipment inspection (PSI). If there is an issue with A5191HRTPG-XTP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The A5191HRTPG-XTP part is unused and in its original packaging.

Return procedure for A5191HRTPG-XTP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…