Allegro MicroSystems A5931GESTR-T
- Part No.:
- A5931GESTR-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
A5931GESTR-T.pdf
- Description:
- SENSORLESS SINUSOIDAL FAN DRIVER
- Quantity:
- Payment:

- Shipping:

Inventory:8,990
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Product details
Overview
A5931GESTR-T from Allegro MicroSystems is a three-phase sensorless sinusoidal fan driver IC designed for high-speed server fans, delivering 3 A motor phase current, closed-loop speed control via configurable EEPROM-based speed curve, and integrated I²C interface. It eliminates Hall sensors, supports PWM or analog speed demand input (PWM mode only for G version), and operates from –40°C to 105°C in a 24-contact 4 mm × 4 mm QFN package with exposed thermal pad.
For engineers reviewing the A5931GESTR-T datasheet, A5931GESTR-T pinout, A5931GESTR-T application, or A5931GESTR-T equivalent, this page provides verified technical context, validated pin functions, confirmed thermal and electrical specifications, and real-world fan control use cases - all specific to the A5931GESTR-T G-version QFN variant.
Technical Context
The A5931GESTR-T implements sensorless back-EMF detection for rotor position estimation and applies sinusoidal modulation at 24.4 kHz typical PWM frequency to minimize audible noise and mechanical vibration. Its closed-loop speed control uses a 9-bit duty-cycle input (6–100 kHz range) converted into RPM demand based on EEPROM-configured slope and offset parameters.
Integrated protection includes overcurrent detection (6.5 A threshold), thermal shutdown (165°C typical), lock detection with programmable RD output behavior, soft start, standby mode, and shorted-load protection. The device features low RDS(ON) power MOSFETs (210 mΩ typical at 25°C) and supports I²C communication using SPD (SCL) and FG (SDA) pins with 7-bit slave address 0x55.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 5–16 V DC - powers internal logic and gate drivers; UVLO triggers at 4.4 V typical to prevent erratic startup. |
| Motor Phase Current | 3000 mA max - enables direct drive of high-speed 12 V server fans without external FETs. |
| PWM Input Frequency | 6–100 kHz - supports fast-response speed control while avoiding interference with I²C timing on shared pins. |
| RDS(ON) (Total) | 210 mΩ typical at 25°C - reduces conduction loss and thermal stress during continuous 3 A operation. |
| Operating Temperature | –40°C to +105°C - qualified for industrial-grade server fan environments with no derating up to 105°C ambient. |
| I²C Slave Address | 0x55 (7-bit) - enables multi-device bus configuration and EEPROM programming or real-time serial speed control. |
| Thermal Resistance θJA | 45 °C/W - measured on 2-layer PCB with 1-in² copper; defines maximum power dissipation before junction exceeds 150°C. |
Pinout & Package
Package: 24-contact QFN (ES), 4 mm × 4 mm × 0.75 mm, lead-free with 100% matte-tin plating and exposed thermal pad for enhanced heat dissipation.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1, 23 | GND | Power and signal reference ground; connects to PCB thermal pad for low-impedance return path. |
| 2, 3 | FG, RD | Open-drain outputs: FG delivers tachometer signal (2 pulses/rev); RD indicates rotor lock fault per EEPROM settings. |
| 4, 21 | DIR, CTAP | DIR controls rotation direction (A→B→C or A→C→B); CTAP is optional Wye-motor common connection with 2 kΩ series resistor. |
| 6, 13 | LSS | Low-side source node - connects to source terminals of internal low-side MOSFETs; must be tied to GND. |
| 7, 9, 12 | OUTA, OUTB, OUTC | Three-phase motor outputs - deliver sinusoidally modulated gate drive to external motor windings. |
| 8, 11 | VBB | Main power supply input (5–16 V) - feeds internal regulators, charge pump, and power stage; requires local 22 µF bulk capacitor. |
| 14, 15, 16, 19 | VCP, CP2, CP1, VREF | VCP/CP1/CP2 form charge pump network for high-side gate drive; VREF supplies stable 2.85 V reference for internal circuits. |
| 17, 18, 20, 22, 24 | NC | No-connect pins - left unconnected per datasheet; not internally bonded or functional. |
| PAD | Thermal Pad | Exposed copper pad - must be soldered to large PCB copper area for thermal management and EMI reduction. |
Key Features
| Feature | Design Value |
|---|---|
| Sensorless sinusoidal drive | Eliminates Hall sensors and associated PCB routing; reduces vibration and acoustic noise in high-RPM server fans. |
| Configurable EEPROM speed curve | Enables application-specific fan profiles (min/max RPM, slope, hysteresis) without MCU firmware or external components. |
| I²C dual-function interface | Uses SPD/FG pins for both speed demand input and serial communication - saves pins and simplifies system integration. |
| Integrated protection suite | Includes lock detection with restart, overcurrent limit (6.5 A), thermal shutdown (165°C), undervoltage lockout, and short-circuit protection. |
| Standby mode via SPD pin | Holding SPD low > lock-off time disables motor and reduces quiescent current to ≤100 µA - ideal for energy-efficient server power states. |
Applications
| Server Fan Control | Data Center Thermal Management |
|---|---|
|
Use Scenario: High-density 1U/2U rack servers requiring silent, reliable cooling under variable thermal loads. IC Role / Device Role / Timing Role: Primary three-phase motor driver executing sensorless sinusoidal commutation and closed-loop RPM regulation. Use Value: Reduces audible noise by >10 dB(A) vs. trapezoidal drives and eliminates Hall sensor failure points in long-life deployments. |
Use Scenario: Multi-fan chassis with centralized thermal monitoring where individual fan speeds are dynamically adjusted. IC Role / Device Role / Timing Role: Standalone speed controller receiving PWM commands from BMC; reports tach feedback via FG pin. Use Value: Enables precise airflow matching to CPU/GPU temperature gradients without adding microcontroller overhead or BOM cost. |
| Industrial Rack-Mount Enclosures | Network Switch Cooling Systems |
|
Use Scenario: Fan-cooled industrial computing enclosures operating continuously in harsh ambient conditions (–40°C to 105°C). IC Role / Device Role / Timing Role: Robust motor driver with thermal shutdown, overcurrent protection, and EEPROM-retained calibration across temperature extremes. Use Value: Ensures uninterrupted operation during thermal transients and prevents field failures due to motor stall or overload. |
Use Scenario: High-port-count Ethernet switches with multiple high-RPM fans requiring coordinated speed ramping and fault reporting. IC Role / Device Role / Timing Role: Fault-aware driver providing RD output for rotor lock detection and FG pulse train for speed verification. Use Value: Enables switch firmware to detect and isolate failed fans automatically, maintaining safe thermal margins during maintenance windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar three-phase sensorless fan driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A5931GLPTR-T | Same IC die, but in 16-lead TSSOP (LP) package with lower θJA (35 °C/W) and identical G-version specs. | Preferred for space-constrained layouts where QFN reflow is impractical; same EEPROM map and feature set. | Select when board assembly favors TSSOP or thermal performance on smaller copper areas is critical. |
| MP6532GQ-Z | Monolithic 3-phase BLDC driver with Hall/sensorless modes; 2.5 A rating, no integrated EEPROM; requires external MCU for speed curve. | Needs external microcontroller and additional passives for closed-loop control - increases BOM count and firmware complexity. | Choose only if sensor fusion (Hall + back-EMF) is required or if existing design already uses MP6532 ecosystem. |
Compared with A5931GESTR-T, the A5931GLPTR-T offers identical functionality in a different package with better thermal resistance but larger footprint, while the MP6532GQ-Z lacks on-chip EEPROM and closed-loop autonomy - requiring external intelligence to replicate A5931GESTR-T's plug-and-play fan control capability.
Availability
A5931GESTR-T is available at Aetrix Electronics and suitable for server fan control, data center thermal management, and industrial rack-mount enclosure cooling requiring stable component supply, long-lifecycle support, and qualified industrial temperature operation.
Supply support for A5931GESTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer of high-performance magnetic sensing and power IC solutions, specializing in motion control, energy efficiency, and reliability for automotive and industrial markets.
The A5931 product line targets high-speed, low-noise cooling systems - specifically engineered to replace Hall-based fan controllers in servers and networking equipment with fully integrated, sensorless, and programmable alternatives.
FAQ
What is the maximum motor phase current supported by the A5931GESTR-T?
The A5931GESTR-T supports up to 3000 mA motor phase current in sinusoidal running mode, as specified in the Recommended Operational Range table. This rating assumes proper PCB thermal design (θJA = 45 °C/W) and operation within the –40°C to +105°C ambient range. Exceeding 3 A may trigger overcurrent protection or cause thermal shutdown.
Does the A5931GESTR-T support analog voltage speed control like the K-version parts?
No, the A5931GESTR-T is a G-version part and supports PWM duty-cycle speed demand only. Analog voltage control (via SPD pin) is exclusive to K-version variants such as A5931KLPTR-T, which include an internal 9-bit ADC. The A5931GESTR-T interprets SPD input strictly as a logic-level PWM signal with 6–100 kHz frequency range.
Can the A5931GESTR-T operate without programming its EEPROM?
Yes, the A5931GESTR-T powers up with factory-default EEPROM settings enabling basic closed-loop operation: MINSPD = 2000 rpm, SPDSLP1 = 2243, DCON = 10%, and other parameters preconfigured for generic fan use. Full customization (e.g., custom speed curves or RD behavior) requires EEPROM programming via I²C or Allegro EVB software.
What is the function of the DIR pin on the A5931GESTR-T?
The DIR pin on the A5931GESTR-T controls motor rotation direction: logic high sequences outputs A→B→C (forward), logic low sequences A→C→B (reverse). It is present only on the ES (QFN) package. DIR is internally pulled up to VREF via 100 kΩ; for noise immunity, Allegro recommends externally tying it to GND or VREF rather than leaving it floating.
How does the A5931GESTR-T handle rotor lock detection and recovery?
The A5931GESTR-T detects rotor lock via back-EMF monitoring and asserts the RD pin high after two consecutive lock events (configurable via LOCKEVT EEPROM bit). Recovery occurs automatically after the programmed tOFF timeout, followed by a soft-start sequence. Lock detection is active during run and startup, and RD behavior (blanking, delay, thresholds) is fully EEPROM-configurable.
A5931GESTR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Motor Type - Stepper:
- Multiphase
- Motor Type - AC, DC:
- Brushless DC (BLDC)
- Function:
- Driver - Fully Integrated, Control and Power Stage
- Output Configuration:
- Half Bridge (3)
- Interface:
- Analog, I2C, PWM
- Technology:
- Power MOSFET
- Step Resolution:
- -
- Applications:
- Fan Motor Driver
- Current - Output:
- 3A
- Voltage - Supply:
- 5V ~ 16V
- Voltage - Load:
- -
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QFN (4x4)
A5931GESTR-T FAQ
1.How can I place an order for A5931GESTR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A5931GESTR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A5931GESTR-T reliable?
The price and inventory of A5931GESTR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A5931GESTR-T is usually 5 days.
3.What payment methods are accepted for A5931GESTR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A5931GESTR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A5931GESTR-T?
A5931GESTR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A5931GESTR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A5931GESTR-T?
For technical support, including A5931GESTR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A5931GESTR-T requirements.
6.How does Aetrix verify that A5931GESTR-T is sourced from the original manufacturer or authorized distributors?
All A5931GESTR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A5931GESTR-T meets industry standards.
7.What is the process for return or replacement of A5931GESTR-T?
All A5931GESTR-T units undergo pre-shipment inspection (PSI). If there is an issue with A5931GESTR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A5931GESTR-T part is unused and in its original packaging.
Return procedure for A5931GESTR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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