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Allegro MicroSystems A5957GESTR-T
- Part No.:
- A5957GESTR-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
A5957GESTR-T.pdf
- Description:
- IC MOTOR DRIVER 5.5V-50V 20QFN
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
A5957GESTR-T from Allegro MicroSystems is a discontinued full-bridge PWM gate driver IC designed for pulse-width-modulated control of DC motors using external N-channel MOSFETs. It operates up to 50 V, integrates synchronous rectification, adjustable off-time/blank-time, current-limit regulation via VREF/SENSE, and provides VDS protection, thermal shutdown with hysteresis, and UVLO - deployed in industrial motor drives requiring robust overcurrent and fault management.
For engineers reviewing the A5957GESTR-T datasheet, A5957GESTR-T pinout, A5957GESTR-T application, or A5957GESTR-T equivalent, this page delivers verified technical context, validated pin functions, confirmed alternatives (A4955, A4956), real-world motor-control use cases, and supply-status clarity for legacy design support and obsolescence planning.
Technical Context
The A5957GESTR-T implements fixed-off-time PWM current control with blank-time blanking to suppress false overcurrent detection during MOSFET switching transients. Its internal charge pump enables high-side N-MOSFET drive above VBB, while synchronous rectification logic reduces conduction losses during slow-decay operation.
Control logic supports PHASE/ENABLE/SLEEPn inputs for forward/reverse/brake/standby states, with OCLn open-drain flag indicating either VDS fault (AIOUT = 0 V) or active current limiting (AIOUT > 0 V). Protection includes VDS monitoring with RC-configurable blanking, thermal shutdown at 150–185 °C with 30 °C hysteresis, and UVLO activation at 5.1–5.4 V with 200–350 mV hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VBB Max | 50 V - Supports 48 V DC motor rails with margin for inductive kickback |
| Gate Drive Voltage | 6.5–7.5 V (typ.) - Sufficient to fully enhance standard N-channel MOSFETs at VBB ≥ 8 V |
| Fixed Off-Time | 30 µs (typ., RRC = 30 kΩ, CRC = 1 nF) - Sets peak-current chopping frequency and thermal duty cycle |
| Blank-Time | 2.1–3.9 µs (typ.) - Suppresses false OCLn trips from diode reverse recovery and load capacitance transients |
| VDS Threshold | 2 V - Triggers latch-off on MOSFET overvoltage events (e.g., shoot-through or avalanche) |
| Thermal Shutdown | 150–185 °C TJ with 30 °C hysteresis - Prevents permanent die damage during overload or poor heatsinking |
| AIOUT Gain | 9–11 V/V - Provides scalable analog current feedback proportional to VSENSE for closed-loop control |
Pinout & Package
The A5957GESTR-T is supplied in a 20-pin QFN package (ES suffix) measuring 4 × 4 mm with an exposed thermal pad for enhanced power dissipation (RθJA = 37 °C/W on 4-layer PCB).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ISET | Gate drive current programming | Resistor-to-ground sets pull-up (≈30 mA typ.) and pull-down (≈68 mA typ.) gate currents |
| SLEEPn | Standby enable input | Active-low signal disables charge pump, regulator, and outputs; reduces IBB to ≤5 µA |
| SENSE | Current-sense resistor return | Low-side shunt connection point; voltage monitored for PWM current limiting and AIOUT scaling |
| GLB, GLA | Low-side gate drivers | Drive N-MOSFET sources; support synchronous rectification during slow-decay off-time |
| GHB, GHA | High-side gate drivers | Charge-pump-powered outputs for N-MOSFET drains; require external bootstrap or charge-pump caps |
| SB, SA | High-side bridge references | Return paths for high-side drivers; tied to respective MOSFET source nodes |
| VCP | Charge pump reservoir | Connects to external capacitor to generate voltage > VBB for high-side gate drive |
| CP1, CP2 | Charge pump terminals | Internal flying-capacitor connections; require external ceramic caps per datasheet layout guidelines |
| VBB | Main supply input | Motor power rail input (5.5–50 V); powers internal regulator, gate drivers, and logic |
| GND | Power and signal ground | Common reference for SENSE, logic, and gate-drive return paths; connects to exposed thermal pad |
| AIOUT | Analog current monitor output | 10× amplified and sample-and-held VSENSE; droops ≤1 mV/µs; zeroed during VDS faults |
| OCLn | Open-drain fault flag | Pulled low for overcurrent (VREF-based) or VDS fault; released after tOCLn (300–600 µs) or reset via SLEEPn/UVLO |
| VREF | Current-limit reference input | 0–2.5 V analog input setting peak current threshold: IPEAK = VREF / (10 × RSENSE) |
| ENABLE | Digital enable input | Active-high control enabling PWM operation; disables outputs when low |
| PHASE | Direction control input | Defines H-bridge polarity: PHASE = 1 → OUTA = H, OUTB = L (forward); PHASE = 0 → reverse |
| RC | Timing network node | External R+C sets both fixed off-time (tOFF) and blank-time (tBLK) for current control loop |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous rectification | Reduces power loss during slow-decay by turning on complementary low-side MOSFET instead of freewheeling through body diode |
| Adjustable gate drive strength | ISET resistor selects gate current (pull-up/pull-down ratio ~1:2), optimizing switching speed vs. EMI for specific MOSFETs |
| VDS fault protection with blanking | Monitors MOSFET VDS only after RC-configurable blank time, preventing false trips during turn-on transients |
| Two-mode overcurrent indication | OCLn + AIOUT jointly distinguish between active current limiting (AIOUT > 0 V) and VDS fault (AIOUT = 0 V) |
| Sample-and-hold AIOUT | Captures peak SENSE voltage during valid current flow; holds value for controller sampling despite PWM ripple |
Applications
| Industrial Conveyor Control | Automated Gate Actuator |
|---|---|
Use Scenario: Precise speed and direction control of 24–48 V DC belt conveyors in packaging lines with variable load inertia. IC Role / Device Role / Timing Role: Full-bridge gate driver managing external N-MOSFET H-bridge; executes PHASE/ENABLE-based motion sequencing and fixed-off-time current limiting. Use Value: Synchronous rectification cuts conduction losses by ~30% vs. diode freewheeling; VDS protection prevents MOSFET failure during jam-induced stall currents. | Use Scenario: Bidirectional actuation of heavy-duty swing gates in access control systems with stall detection and soft-start. IC Role / Device Role / Timing Role: PWM-controlled H-bridge driver with AIOUT-based current profiling and OCLn-triggered emergency stop on overcurrent or short-circuit. Use Value: Adjustable blank-time eliminates false OCLn trips from gate capacitance charging; thermal shutdown prevents overheating during repeated stall cycles. |
| Medical Infusion Pump Drive | Robotic Joint Motor Controller |
Use Scenario: Low-noise, precise microstepping-equivalent control of peristaltic pump DC motors in Class II medical devices. IC Role / Device Role / Timing Role: Gate driver implementing slow-decay PWM with AIOUT feedback for closed-loop current regulation and stall detection. Use Value: Sample-and-hold AIOUT provides stable current measurement independent of PWM duty cycle; UVLO ensures safe power-up sequencing. | Use Scenario: Compact, high-efficiency motor drive for articulated robotic joints requiring rapid direction reversal and torque limiting. IC Role / Device Role / Timing Role: Full-bridge controller executing PHASE-flip commutation with real-time current limiting via VREF-adjusted off-time. Use Value: Dead-time (1000 ns) prevents shoot-through; exposed thermal pad sustains 2.5 W continuous dissipation in space-constrained enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar full-bridge gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A4955 | Integrated current sense amplifier; no external VREF required; lower max VBB (40 V) | Better suited for cost-sensitive, lower-voltage (<40 V) motor drives where integrated sensing simplifies BOM | Select A4955 when replacing A5957GESTR-T in <40 V systems and board space allows rework for different pinout and sensing architecture |
| A4956 | Higher VBB rating (50 V same as A5957); includes integrated current sense and VDS protection; different timing architecture (programmable off-time vs. fixed) | Direct functional upgrade path with enhanced integration; requires validation of new RC timing behavior and AIOUT interface | Select A4956 for new designs needing 50 V capability and reduced external components, accepting layout changes and firmware timing updates |
Compared with A5957GESTR-T, A4955 offers simplified current sensing but sacrifices 50 V operation and VDS blanking flexibility, while A4956 retains 50 V rating and adds integration - yet replaces fixed off-time with programmable timing, demanding control-loop recalibration.
Availability
A5957GESTR-T is available at Aetrix Electronics and suitable for industrial motor control, automated actuation, medical infusion pumps, and robotic joint drives requiring stable component supply for legacy system maintenance and repair.
Supply support for A5957GESTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer of high-performance Hall-effect sensors, motor drivers, and power ICs, founded in 1989 and headquartered in Manchester, NH.
The A5957GESTR-T belongs to Allegro's full-bridge PWM gate driver product line, engineered for reliable, high-efficiency control of external N-channel MOSFET H-bridges in demanding DC motor applications across industrial, medical, and automation markets.
FAQ
Is the A5957GESTR-T still in production?
No, the A5957GESTR-T is a discontinued product. Allegro MicroSystems announced discontinuation effective August 13, 2020. It is no longer manufactured, and samples are unavailable. Aetrix Electronics supplies remaining authorized inventory for legacy design support and repair, with full traceability and lifecycle coordination.
What are the key functional differences between A5957GESTR-T and its recommended alternatives A4955 and A4956?
The A5957GESTR-T uses external VREF and SENSE for current limiting with fixed off-time, while A4955 integrates the current sense amplifier (no VREF needed) but limits VBB to 40 V. The A4956 matches the 50 V rating and adds integrated sensing and VDS protection, but replaces fixed off-time with programmable timing - requiring control-loop validation when migrating from A5957GESTR-T.
Can the A5957GESTR-T drive P-channel high-side MOSFETs?
No, the A5957GESTR-T is specifically designed for all-N-channel external MOSFET bridges. Its high-side drivers (GHA/GHB) rely on an internal charge pump to generate gate voltage above VBB, making them incompatible with P-channel devices, which require gate drive below source potential. Using P-MOSFETs would violate the device's architecture and disable synchronous rectification.
How does the A5957GESTR-T handle braking current, and why isn't it current-limited during brake mode?
During braking, current flows through the body diodes or external freewheeling paths, bypassing the SENSE resistor. Since the A5957GESTR-T regulates current only via VSENSE, braking current remains unregulated. Peak braking current approximates VBEMF / RMOTOR, so external MOSFET SOA and thermal design must accommodate worst-case inertial loads without relying on A5957GESTR-T current limiting.
What is the purpose of the RC pin on the A5957GESTR-T, and how do R and C values affect operation?
The RC pin sets both fixed off-time (tOFF) and blank-time (tBLK) using an external resistor and capacitor. tOFF ≈ RRC × CRC + dead time (1000 ns); tBLK ≈ 2.6 µs × CRC(nF) × e^(3.6/RRC(kΩ)). Selecting RRC = 30 kΩ and CRC = 1 nF yields tOFF ≈ 30 µs and tBLK ≈ 3 µs - balancing current regulation responsiveness against noise immunity during MOSFET switching transitions in the A5957GESTR-T.
A5957GESTR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushed DC
- Function:
- Controller - Commutation, Direction Management
- Output Configuration:
- Pre-Driver - Half Bridge (2)
- Interface:
- Parallel
- Technology:
- NMOS
- Step Resolution:
- -
- Applications:
- General Purpose
- Current - Output:
- -
- Voltage - Supply:
- 5.5V ~ 50V
- Voltage - Load:
- -
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN-EP (4x4)
A5957GESTR-T FAQ
1.How can I place an order for A5957GESTR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A5957GESTR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A5957GESTR-T reliable?
The price and inventory of A5957GESTR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A5957GESTR-T is usually 5 days.
3.What payment methods are accepted for A5957GESTR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A5957GESTR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A5957GESTR-T?
A5957GESTR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A5957GESTR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A5957GESTR-T?
For technical support, including A5957GESTR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A5957GESTR-T requirements.
6.How does Aetrix verify that A5957GESTR-T is sourced from the original manufacturer or authorized distributors?
All A5957GESTR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A5957GESTR-T meets industry standards.
7.What is the process for return or replacement of A5957GESTR-T?
All A5957GESTR-T units undergo pre-shipment inspection (PSI). If there is an issue with A5957GESTR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A5957GESTR-T part is unused and in its original packaging.
Return procedure for A5957GESTR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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