NXP Semiconductors A5G35H110N-3400
- Part No.:
- A5G35H110N-3400
- Manufacturer:
- NXP Semiconductors
- Category:
- Single FETs, MOSFETs
- Package:
- 6-LDFN Exposed Pad
- Datasheet:
-
A5G35H110N-3400.pdf
- Description:
- RF MOSFET 48V 6DFN
- Quantity:
- Payment:

- Shipping:

Inventory:6,976
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
A5G35H110N from NXP Semiconductors is a 15.1 W asymmetrical Doherty RF power GaN amplifier designed for 5G massive MIMO active antenna systems in cellular base stations, operating across 3300–3700 MHz with 57.6% drain efficiency at 3300 MHz, 14.8 dB power gain, and –27.9 dBc ACPR under W-CDMA modulation.
For engineers reviewing the A5G35H110N datasheet, A5G35H110N pinout, A5G35H110N application, or A5G35H110N equivalent, this page delivers verified specifications, thermal performance data, ruggedness validation under 400 MHz ISBW at 55 Vdc, bias sequencing guidance, and real-world design context for 3.5 GHz 5G infrastructure deployment.
Technical Context
The A5G35H110N implements a dual-path GaN-on-SiC Doherty architecture with separate carrier and peaking transistors, internally matched for 50 Ω operation across 3300–3700 MHz. It uses depletion-mode GaN HEMTs requiring negative gate bias (VGSB = –4.1 Vdc, VGSA(Q) = –2.4 Vdc typical) and operates at 48 Vdc drain supply.
Its thermal design targets high-power reliability: RθJC (IR) = 2.8 °C/W measured at PD = 14.2 W, with maximum channel temperature limited to 225 °C. The device sustains 30.2 W avg. modulated output under 10 dB PAR AWGN stress with no degradation, confirming broadband ruggedness for real-world 5G signal conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Range | 3300–3700 MHz - Fully characterized and guaranteed performance band for 3.5 GHz 5G TDD deployments. |
| Output Power (Avg.) | 15.1 W - Delivers linearized output for single-carrier W-CDMA at 9.9 dB PAR, enabling high-efficiency 5G NR uplink. |
| Drain Efficiency (ηD) | 57.6% @ 3300 MHz - Reduces thermal load and power supply demand in densely packed active antenna arrays. |
| Power Gain (Gps) | 15.4 dB @ 3400 MHz - Enables compact driver stage design while maintaining system-level linearity after digital predistortion. |
| ACPR (W-CDMA) | –29.3 dBc @ 3400 MHz - Meets stringent 3GPP ACLR requirements for 5G base station transmission without excessive backoff. |
| Thermal Resistance (RθJC) | 2.8 °C/W - Supports high-power density PCB layouts with direct thermal path to heatsink via exposed die paddle. |
| VSWR Tolerance | Withstands extreme broadband output VSWR - critical for active antenna modules where antenna mismatch varies dynamically. |
Pinout & Package
Package: DFN 7 × 6.5 mm surface-mount package with thermally enhanced exposed paddle for low-impedance heat transfer. Designed for reflow soldering per AN1907 guidelines.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 | Ground / Exposed Paddle | Common RF and DC ground reference; electrically and thermally connected to PCB ground plane for optimal EMI control and thermal dissipation. |
| 17 | RF Input | 50 Ω matched input port for carrier + peaking signal injection; requires external DC blocking and bias feed network. |
| 18 | RF Output | 50 Ω matched output port delivering combined Doherty output; designed for direct connection to antenna array feed network. |
| 19 | VDDA (Carrier Drain) | 48 Vdc supply for carrier transistor; must be decoupled locally with low-ESR capacitors near pin. |
| 20 | VGSB (Peaking Gate) | Negative bias control for peaking transistor; set to –4.1 Vdc typical for optimal Doherty load modulation. |
| 21 | VGSA (Carrier Gate) | Negative bias control for carrier transistor; adjusted to achieve IDQA = 70 mA quiescent current. |
| 22 | VDSB (Peaking Drain) | 48 Vdc supply for peaking transistor; independent routing recommended to minimize coupling with carrier drain path. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetrical Doherty Architecture | Optimizes efficiency vs. linearity trade-off for 5G NR signals with high PAPR, enabling >54% average efficiency across full 3.5 GHz band. |
| Internally Matched 50 Ω I/O | Eliminates need for external matching networks at RF ports, reducing bill-of-materials and layout complexity in multi-element antenna modules. |
| High Ruggedness (400 MHz ISBW) | Sustains 30.2 W avg. modulated output under 10 dB PAR AWGN at 55 Vdc with zero degradation - validated for real-world interference and mismatch scenarios. |
| Low AM/PM Distortion | –6° max across 3400–3600 MHz - minimizes EVM degradation in wideband 5G NR channels and simplifies digital predistortion convergence. |
| Thermally Optimized DFN Package | 2.8 °C/W junction-to-case resistance enables >40 W peak power handling in compact form factor suitable for active antenna unit integration. |
Applications
| 5G Massive MIMO Active Antenna Unit (AAU) | 3.5 GHz TDD Macro Base Station |
|---|---|
|
Use Scenario: Integrated into 64T64R active antenna arrays for urban 5G coverage, supporting 100 MHz channel bandwidth and 256-QAM modulation. IC Role / Device Role / Timing Role: Final-stage RF power amplifier delivering 15.1 W avg. output per chain with Doherty efficiency enhancement. Use Value: Enables higher spectral efficiency and cell edge throughput by maintaining ACLR < –29 dBc while operating at 55.7% efficiency at 3400 MHz. |
Use Scenario: Deployed in outdoor macro base stations serving dense residential zones with dynamic traffic loads and variable antenna VSWR. IC Role / Device Role / Timing Role: High-ruggedness GaN PA ensuring uninterrupted operation despite antenna detuning caused by environmental factors. Use Value: Eliminates need for VSWR protection circuitry due to intrinsic tolerance of extreme broadband mismatch, reducing system cost and failure points. |
| 5G NR FDD/TDD Small Cell Remote Radio Head (RRH) | Open RAN Distributed Unit (DU) Front-Haul Interface |
|
Use Scenario: Used in compact, fanless RRH units deployed on street furniture with strict thermal envelope constraints. IC Role / Device Role / Timing Role: Efficient RF power stage minimizing heat generation while meeting 3GPP TS 38.104 conducted output power requirements. Use Value: Achieves 54.3% efficiency at 3600 MHz with only 0.03 dB/°C gain variation over –40°C to +85°C, ensuring stable link budget across ambient conditions. |
Use Scenario: Embedded in Open RAN-compliant DU hardware supporting fronthaul split (Option 7-2x) with low-latency digital beamforming. IC Role / Device Role / Timing Role: Linearized PA stage synchronized with FPGA-based DPD engine for real-time correction of wideband distortion. Use Value: Delivers 0.4 dB gain flatness over 200 MHz bandwidth at 15.1 W avg., enabling accurate wideband channel estimation and beam alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF power amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A5G35H110NT4 | Same die, tape-and-reel packaging (2,500 units/reel); identical electrical and thermal specs; DFN 7 × 6.5 mm footprint. | No functional difference - used for automated SMT assembly; same PCB layout and thermal interface requirements. | Select A5G35H110NT4 for volume production; A5G35H110N is the base part number used for datasheet referencing and design-in. |
| AFGA35H110N | Legacy Airfast variant with identical frequency range and Doherty architecture but lower 52% max efficiency and no 400 MHz ISBW ruggedness validation. | Suitable for less demanding 4G/LTE+ deployments; lacks guaranteed 5G NR linearity and thermal robustness for massive MIMO. | Choose A5G35H110N when designing for 5G NR compliance, high PAR signals, or environments with unpredictable antenna VSWR. |
Compared with A5G35H110NT4 (identical functionality, packaging-only variant) and AFGA35H110N (older generation), the A5G35H110N delivers 5.7% higher peak efficiency, validated 400 MHz ruggedness, and tighter gain flatness - directly enabling higher output power density and reduced cooling overhead in next-gen 5G active antennas.
Availability
A5G35H110N is available at Aetrix Electronics and suitable for 5G massive MIMO active antenna units, 3.5 GHz TDD macro base stations, and Open RAN remote radio heads requiring stable component supply, long-term lifecycle support, and traceable GaN sourcing.
Supply support for A5G35H110N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and communications markets.
The Airfast RF Power product line delivers GaN-based amplifiers optimized for 4G/5G cellular infrastructure, emphasizing high efficiency, broadband operation, and ruggedness in thermally constrained active antenna systems.
FAQ
What is the guaranteed operating frequency range for the A5G35H110N?
The A5G35H110N is fully characterized and performance-guaranteed across 3300–3700 MHz. Operation outside this band is not validated, and NXP does not guarantee specifications such as gain, efficiency, or ACPR beyond these limits. Designers must constrain RF front-end filtering and LO planning to this 400 MHz window to ensure compliance with datasheet performance.
How is bias applied to the A5G35H110N in a Doherty configuration?
The A5G35H110N requires strict bias sequencing: first set both gates to –5 V, then apply 48 Vdc to both drains, then ramp VGSA to achieve IDQA = 70 mA, then set VGSB = –4.1 Vdc. During shutdown, reverse the sequence - remove RF, return gates to –5 V, discharge drains to 0 V, then disable gate supplies. This prevents gate overstress and ensures reliable GaN HEMT operation.
Does the A5G35H110N require external impedance matching networks?
No - the A5G35H110N is internally matched to 50 Ω at both RF input and output ports across 3300–3700 MHz. External matching is unnecessary for standard operation; however, designers must implement proper DC blocking, bias feed, and harmonic filtering per NXP reference circuit guidelines to maintain specified linearity and efficiency.
What thermal interface requirements apply to the A5G35H110N's DFN package?
The A5G35H110N uses a thermally enhanced DFN 7 × 6.5 mm package with an exposed paddle that must be soldered to a large, low-thermal-resistance PCB copper area connected to the system heatsink. Per AN1907, solder paste stencil design and reflow profile must ensure void-free thermal interface; RθJC = 2.8 °C/W assumes full paddle attachment and adequate heatsinking.
Is the A5G35H110N suitable for 5G NR FR1 deployments beyond 3.5 GHz?
No - the A5G35H110N is specifically designed and tested for 3300–3700 MHz operation. While it may function outside this band, NXP provides no performance guarantees for gain, efficiency, ACPR, or ruggedness at frequencies such as 2.6 GHz (n41) or 4.9 GHz (n79). For those bands, consult NXP's A5G26H110N or A5G49H110N variants.
A5G35H110N-3400 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 6-LDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Active
- Technology:
- -
- Configuration:
- -
- Frequency:
- 3.3GHz ~ 3.7GHz
- Gain:
- 15.3dB
- Voltage - Test:
- 48 V
- Current Rating (Amps):
- -
- Noise Figure:
- -
- Current - Test:
- 70 mA
- Power - Output:
- 15.1W
- Voltage - Rated:
- 125 V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-PDFN (7x6.5)
A5G35H110N-3400 FAQ
1.How can I place an order for A5G35H110N-3400 through Aetrix?
Please submit a Request for Quotation (RFQ) for A5G35H110N-3400 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A5G35H110N-3400 reliable?
The price and inventory of A5G35H110N-3400 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A5G35H110N-3400 is usually 5 days.
3.What payment methods are accepted for A5G35H110N-3400?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A5G35H110N-3400 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A5G35H110N-3400?
A5G35H110N-3400 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A5G35H110N-3400 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A5G35H110N-3400?
For technical support, including A5G35H110N-3400 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A5G35H110N-3400 requirements.
6.How does Aetrix verify that A5G35H110N-3400 is sourced from the original manufacturer or authorized distributors?
All A5G35H110N-3400 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A5G35H110N-3400 meets industry standards.
7.What is the process for return or replacement of A5G35H110N-3400?
All A5G35H110N-3400 units undergo pre-shipment inspection (PSI). If there is an issue with A5G35H110N-3400, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A5G35H110N-3400 part is unused and in its original packaging.
Return procedure for A5G35H110N-3400:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
A5G35H110N-3400 Tags

-
3SK294(TE85L,F)
Toshiba Semiconductor and Storage
-
SAV-551+
Mini-Circuits

-
TAV2-501+
Mini-Circuits

-
CE3514M4-C2
CEL

-
AFT05MS004NT1
NXP USA Inc.
-
SAV-541+
Mini-Circuits

-
CE3512K2-C1
CEL

-
AFM907NT1
NXP Semiconductors

-
SKY65050-372LF
Skyworks Solutions Inc.

-
CE3520K3-C1
CEL

-
AFT09MS007NT1
NXP USA Inc.

-
AFT09MS015NT1
NXP USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
