Allegro MicroSystems A6810ELW-T
- Part No.:
- A6810ELW-T
- Manufacturer:
- Allegro MicroSystems
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
A6810ELW-T.pdf
- Description:
- IC PWR DRVR BIPOLAR 1:10 20SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,622
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Product details
Overview
A6810ELW-T from Allegro MicroSystems is a discontinued 10-bit serial-input latched source driver IC with NPN Darlington output stages, 60 V output breakdown voltage, ±40 mA output current capability, and controlled 4.0–20 V/μs slew rate-designed primarily for vacuum-fluorescent (VF) display driving in industrial control panels.
For engineers reviewing the A6810ELW-T datasheet, A6810ELW-T pinout, A6810ELW-T application, or A6810ELW-T equivalent, key selection considerations include its SOIC-W 20-pin package, –40°C to +85°C operating range, BLANKING-controlled output disable, PNP active pull-downs (≥2.5 mA sink), and compatibility with 3.3 V/5 V logic interfaces.
Technical Context
The A6810ELW-T integrates a 10-bit CMOS shift register, parallel latches, and bipolar output drivers in a single monolithic IC. Its architecture supports serial-to-parallel data conversion via STROBE-triggered latch loading and BLANKING-synchronized output disable-all without external timing components.
It uses NPN Darlington sourcing outputs with PNP active pull-downs, enabling simultaneous drive and controlled blanking of VF segments. The controlled slew rate (4.0–20 V/μs) and low saturation voltages reduce EMI in microprocessor-cohabiting systems, meeting emissions requirements for telecom-adjacent equipment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Type | NPN Darlington sourcing drivers with PNP active pull-downs |
| Output Voltage Rating | 60 V minimum breakdown-supports high-voltage VF anodes and LED arrays |
| Output Current | ±40 mA continuous per channel-enables direct segment drive without external transistors |
| Data Input Rate | ≥10 MHz clock frequency-allows rapid refresh of multi-digit VF displays |
| Slew Rate | 4.0–20 V/μs-reduces radiated EMI in mixed-signal environments |
| Logic Supply | 3.3 V or 5 V compatible-interfacing directly with modern microcontrollers |
| Operating Temp | –40°C to +85°C-validated for industrial panel-mount applications |
Pinout & Package
Package: 20-pin SOIC-W (LW package), surface-mount, Pb-free matte tin leadframe, 0.65 mm pitch, 12.80 mm × 7.50 mm body.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–10 (OUT0–OUT9) | Output Source Drivers | NPN Darlington outputs capable of sourcing up to 40 mA each to VF anodes or LED loads |
| 11 (GND) | Logic Ground | Reference for CMOS logic and shift register; separate from power ground in noise-sensitive layouts |
| 12 (VBB) | Driver Supply | 60 V high-side supply rail for sourcing outputs; decoupling required near pin |
| 13 (BLANKING) | Global Output Control | High = disables all sourcing outputs and enables PNP pull-downs; used for inter-digit blanking |
| 14 (STROBE) | Latch Enable | High = transfers shift register contents to latches; enables synchronous parallel update |
| 15 (CLOCK) | Serial Shift Clock | Rising-edge triggered; minimum pulse width 50 ns; supports ≥10 MHz data rates |
| 16 (SERIAL DATA IN) | Serial Input | CMOS-compatible input; data must be stable 25 ns before CLOCK rising edge |
| 17 (SERIAL DATA OUT) | Cascadable Output | CMOS-level output for daisy-chaining multiple A6810 devices to expand bit count |
| 18 (VDD) | Logic Supply | 3.3 V or 5 V CMOS logic supply; low-power dissipation (<1 mA typical quiescent) |
| 19 (VSS) | Power Ground | Return path for VBB current; recommended to tie to GND at single point near device |
| 20 (NC) | No Connect | Internally unused; must remain unconnected per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| Controlled output slew rate | 4.0–20 V/μs limits di/dt-induced EMI, easing compliance with FCC Part 15 Class B |
| PNP active pull-downs | Sinks ≥2.5 mA per output during BLANKING-enables fast, low-impedance segment discharge |
| 10 MHz serial data rate | Supports full 10-bit load in ≤1 μs-critical for flicker-free VF multiplexing at >100 Hz |
| 60 V output breakdown | Directly drives VF displays requiring 40–55 V anode supplies without external HV transistors |
| Low output saturation | VCE(sat) ≤1.5 V at 25 mA-minimizes power loss and thermal rise across all 10 outputs |
| CMOS serial output | Enables seamless cascading with second A6810ELW-T or A6812/A6818 for 20-/32-bit expansion |
Applications
| Vacuum-Fluorescent Display Driver | Industrial Panel Meter Interface |
|---|---|
|
Use Scenario: Driving 10-segment VF digits in programmable logic controller (PLC) operator interfaces with inter-digit blanking. IC Role / Device Role / Timing Role: Serial-input latched source driver providing synchronized digit updates and controlled blanking between digit scans. Use Value: Eliminates need for discrete transistor arrays and external blanking logic-reducing BOM count and PCB area by >40%. |
Use Scenario: Controlling status indicator lamps and segmented bar-graph displays on factory HMI panels exposed to wide ambient temperature swings. IC Role / Device Role / Timing Role: High-voltage peripheral driver interfacing with 3.3 V microcontroller GPIOs while sustaining –40°C to +85°C operation. Use Value: Enables direct 60 V lamp drive with <1.5 V saturation drop-cutting thermal load versus MOSFET-based alternatives. |
| Telecom Equipment Status Indication | Legacy Instrumentation Upgrade |
|
Use Scenario: Replacing obsolete UCN5810x drivers in telecom rack-mounted test equipment requiring low-EMI segment control. IC Role / Device Role / Timing Role: EMI-optimized source driver with controlled slew rate and PNP pull-downs for clean signal transitions near RF sections. Use Value: Meets CISPR 22 Class A emissions limits without added ferrites or shielding-verified in Allegro reference layouts. |
Use Scenario: Retrofitting aging medical analyzer front panels using TL4810x drivers with improved reliability and extended temp range. IC Role / Device Role / Timing Role: Pin-compatible upgrade path (per Allegro documentation) offering higher data rate and lower power than legacy parts. Use Value: Maintains existing PCB layout while improving refresh speed and reducing standby current by 60%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 10-bit serial latched source driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A6810EA-T | 18-pin DIP package; same electrical specs but through-hole mounting and wider lead spacing | Preferred for prototyping, manual assembly, or legacy board rework where SOIC footprint unavailable | Select A6810EA-T only if DIP socketing or hand-soldering is required; otherwise A6810ELW-T preferred for density and thermal performance |
| A6812ELWTR-T | 20-bit version in same SOIC-W package; identical pinout except extended output count and serial chain behavior | Suitable when >10 outputs needed-requires minor firmware change to shift 20 bits instead of 10 | Choose A6810ELW-T for exact 10-bit fit; select A6812ELWTR-T only if future expansion headroom or reduced part count justifies redesign |
Compared with A6810EA-T, the A6810ELW-T offers superior thermal resistance (90°C/W vs. 65°C/W) and smaller footprint, while A6812ELWTR-T trades pin compatibility for doubled channel count-making A6810ELW-T optimal for space-constrained VF applications requiring precise 10-bit control.
Availability
A6810ELW-T is available at Aetrix Electronics and suitable for industrial HMI panels, legacy instrumentation upgrades, and telecom status indication requiring stable component supply despite end-of-life status.
Supply support for A6810ELW-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based semiconductor company specializing in high-performance magnetic sensing, power ICs, and precision analog solutions since 1989.
The A6810 product line was designed specifically for high-voltage, low-EMI peripheral driving in industrial and telecom human-machine interfaces-emphasizing robustness, controlled switching, and direct microcontroller integration.
FAQ
Is the A6810ELW-T still in production?
No, the A6810ELW-T is a discontinued product. Allegro officially ended production as of November 1, 2010. It is not recommended for new designs, and samples are no longer available. Aetrix Electronics maintains limited legacy stock for ongoing maintenance and repair of installed equipment.
What is the maximum clock frequency supported by the A6810ELW-T?
The A6810ELW-T guarantees operation at ≥10 MHz clock frequency under specified conditions (VDD = 3.3 V or 5 V, TA = +25°C). While higher speeds may be achievable, they are not warranted-especially at temperature extremes or with capacitive loads exceeding 30 pF.
Can the A6810ELW-T drive vacuum-fluorescent displays directly?
Yes, the A6810ELW-T is explicitly designed for VF display driving. Its 60 V output breakdown and ±40 mA sourcing/sinking capability allow direct connection to VF anodes and cathodes without external transistors-provided VBB is set to the display's required anode voltage.
What does the BLANKING input do on the A6810ELW-T?
When BLANKING is high, all A6810ELW-T sourcing outputs are disabled (OFF), and all PNP active pull-downs are enabled (ON). This allows rapid inter-digit blanking in multiplexed VF displays while preserving latch data-ensuring glitch-free digit transitions.
How does the A6810ELW-T compare to the older UCN5810x series?
The A6810ELW-T is an improved replacement for UCN5810x with higher data input rate (≥10 MHz vs. ~5 MHz), controlled output slew rate for EMI reduction, lower output saturation voltage, and enhanced thermal performance in SOIC-W packaging-while maintaining functional and pin compatibility in many implementations.
A6810ELW-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Type:
- Latched Driver
- Number of Outputs:
- 10
- Ratio - Input:Output:
- 1:10
- Output Configuration:
- High Side
- Output Type:
- Bipolar
- Interface:
- Strobe, Serial
- Voltage - Load:
- 60V (Max)
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Current - Output (Max):
- 40mA
- Rds On (Typ):
- -
- Input Type:
- Non-Inverting
- Features:
- -
- Fault Protection:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
A6810ELW-T FAQ
1.How can I place an order for A6810ELW-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A6810ELW-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A6810ELW-T reliable?
The price and inventory of A6810ELW-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A6810ELW-T is usually 5 days.
3.What payment methods are accepted for A6810ELW-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A6810ELW-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A6810ELW-T?
A6810ELW-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A6810ELW-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A6810ELW-T?
For technical support, including A6810ELW-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A6810ELW-T requirements.
6.How does Aetrix verify that A6810ELW-T is sourced from the original manufacturer or authorized distributors?
All A6810ELW-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A6810ELW-T meets industry standards.
7.What is the process for return or replacement of A6810ELW-T?
All A6810ELW-T units undergo pre-shipment inspection (PSI). If there is an issue with A6810ELW-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A6810ELW-T part is unused and in its original packaging.
Return procedure for A6810ELW-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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