Allegro MicroSystems A81805KESJSR-1
- Part No.:
- A81805KESJSR-1
- Manufacturer:
- Allegro MicroSystems
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
A81805KESJSR-1.pdf
- Description:
- IC REG BUCK 5V 2.5A 20QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
A81805KESJSR-1 from Allegro MicroSystems is a 40 V, 2.5 A synchronous buck regulator delivering a fixed 5 V output with ±1.5% accuracy across −40°C to 150°C, featuring ultra-low 7.5 µA no-load quiescent current, spread-spectrum EMI reduction, and programmable 400 kHz–2.5 MHz switching frequency - deployed in automotive infotainment and ADAS power rails.
For engineers reviewing the A81805KESJSR-1 datasheet, A81805KESJSR-1 pinout, A81805KESJSR-1 application, or A81805KESJSR-1 equivalent, key selection criteria include its AEC-Q100 Grade 0 qualification, 3.5–36 V input range, integrated loop compensation, LP/PWM auto-transition behavior, and wettable-flank QFN thermal performance.
Technical Context
The A81805KESJSR-1 implements fixed-frequency peak current-mode control with internal slope compensation and programmable oscillator via FSET resistor or external SYNC clock (400 kHz–2.5 MHz). Its PLL-based synchronization supports fSYNC above or below fOSC without mode disruption.
It integrates high-side (170 mΩ) and low-side (130 mΩ) N-channel MOSFETs, an internal VCC LDO powered from VIN or VOUT, and dual-path protection logic covering pulse-by-pulse current limit, hiccup-mode short-circuit, BOOT voltage fault, VIN UVLO (3.55 V turn-on), and thermal shutdown at 170°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VOUT | Fixed 5 V output, ±1.5% accuracy over −40°C to 150°C - ensures stable MCU/SOC core rail under automotive thermal stress. |
| VIN Range | 3.5 V to 36 V operating, 40 V transient - supports cold-crank (6.5 V) and load-dump (40 V) conditions per ISO 7637-2. |
| IOUT Continuous | 2.5 A max - powers multi-rail domain controllers without external boost stages. |
| IQ (No Load) | 7.5 µA from VIN at 12 V - enables >10-year battery hold-up in always-on telematics modules. |
| fSW Programmability | 400 kHz to 2.5 MHz via FSET resistor or SYNC pin - allows EMI band avoidance and layout optimization for space-constrained PCBs. |
| EMI Mitigation | Triangular spread spectrum (±5% dither) - reduces peak radiated emissions to meet CISPR 25 Class 5 limits. |
| Protection Suite | Includes hiccup-mode short-circuit, BOOT OV/UV, VOUT OVP/UVP (±94 mV hysteresis), and thermal shutdown with 20°C hysteresis. |
Pinout & Package
Supplied in a thermally enhanced 20-pin wettable flank QFN package (4 mm × 4 mm × 0.75 mm, exposed thermal pad), optimized for automotive PCB assembly and thermal dissipation (RθJA = 31°C/W on evaluation board).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VOUT | Output voltage feedback node | Connects directly to output capacitor; powers internal VOUT-LDO for VCC generation once regulation is achieved. |
| 3 GND | Analog ground reference | Separate from PGND pins; must be routed to quiet analog ground plane to avoid noise coupling into error amplifier. |
| 4 FSET | Switching frequency programming input | Resistor-to-GND sets fSW; tie to VCC for fixed 2.2 MHz - eliminates need for external clock source in cost-sensitive designs. |
| 5 SYNC | External clock synchronization input | Accepts 400 kHz–2.5 MHz square wave; forces PWM mode and applies dither to synchronized frequency - critical for multi-regulator EMI coherence. |
| 6,7 PGND | Power ground return path | Low-inductance connection point for SW, VIN, and BOOT capacitors; must be tied to exposed thermal pad for optimal thermal and EMI performance. |
| 9–11 VIN | Main input voltage supply | Three parallel pins reduce IR drop and improve current sharing; requires local 100 nF ceramic bypass close to pin 9. |
| 12 EN | Hysteretic enable control input | 1.2 V typical threshold with 200 mV hysteresis; draws only 1 µA in shutdown - enables precise system-level power sequencing. |
| 13 PGOOD | Open-drain power-good status output | Asserts low if VOUT falls below 4.625 V or rises above 5.375 V; includes 120 µs UV delay and 310 µs OV delay for glitch immunity. |
| 15 VCC | Internal regulator bypass | Requires 4.7 µF ceramic capacitor to PGND; supplies bias for gate drivers and control logic - decoupling prevents startup instability. |
| 16 BOOT | High-side MOSFET gate drive supply | Connected via 100 nF capacitor to SW node; regulates at 3.2 V typical - ensures robust high-side conduction during low-duty-cycle operation. |
| 17–20 SW | Switch node output | Four paralleled pins minimize trace inductance; connects to power inductor and BOOT capacitor - critical for minimizing voltage spikes and EMI. |
| PAD | Exposed thermal pad | Mandatory connection to PGND plane; accounts for >75% of total heat transfer - omission causes >30°C junction rise under full load. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated loop compensation | Eliminates three external RC components - reduces BOM count and layout sensitivity while maintaining phase margin >45° across line/load/temp. |
| Pre-bias startup capability | Allows safe start-up into pre-charged output rail - essential for hot-swap and redundant power systems without output voltage overshoot. |
| Maximized duty cycle at low VIN | Extends conduction time during cold-crank (6.5 V); maintains 5 V output down to VIN = 5.8 V at full load - avoids brownout in engine-start scenarios. |
| Robust FMEA coverage | Detects pin open/short faults and internal component failures - meets ASIL-B diagnostic coverage requirements for automotive safety subsystems. |
| Ultra-low IQ LP mode | 6–7.5 µA no-load draw with automatic PWM-to-LP transition at ~700 mA peak inductor current - extends battery life without manual mode control. |
Applications
| Infotainment Power Supply | ADAS Camera Module Rail |
|---|---|
|
Use Scenario: Powers SoC, display interface, and audio codecs in vehicle head units with 12 V battery input and strict EMC limits. IC Role / Device Role / Timing Role: Primary 5 V intermediate bus regulator delivering 2.5 A with spread-spectrum switching to pass CISPR 25 Class 5 radiated emissions. Use Value: Eliminates need for external EMI filters and reduces heatsink area by 40% versus discrete controller + MOSFET solutions. |
Use Scenario: Supplies image sensor and ISP in forward-facing camera modules requiring continuous operation during ignition cycles. IC Role / Device Role / Timing Role: Always-on 5 V rail with <7.5 µA quiescent current and pre-bias startup - sustains power during stop-start engine events. Use Value: Enables >15-year battery-backed operation in parking mode without compromising cold-crank performance. |
| Instrument Cluster Core Supply | Industrial Telematics Tracker |
|
Use Scenario: Generates clean 5 V for microcontroller, CAN transceiver, and TFT backlight driver in digital dashboards. IC Role / Device Role / Timing Role: AEC-Q100 Grade 0 qualified buck regulator with 150°C TJ rating and thermal shutdown hysteresis - survives under-hood ambient up to 105°C. Use Value: Replaces dual-stage (48 V → 12 V → 5 V) conversion with single-stage, improving efficiency by 8% at 1 A load. |
Use Scenario: Powers GPS/GNSS, cellular modem, and flash memory in container tracking devices deployed globally. IC Role / Device Role / Timing Role: Wide-input (3.5–36 V) regulator with 40 V transient tolerance - withstands railway and heavy-equipment battery fluctuations. Use Value: Supports direct connection to 24 V truck/trailer batteries without upstream TVS or DC-DC pre-regulator. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPQ4423AGL-AEC1-P | 3.5–36 V input, 5 V/3 A output, 15 µA IQ, no spread spectrum, QFN-16 | Lacks CISPR 25 Class 5 EMI certification; lower integration (external compensation required) | Preferred where higher output current is needed but EMI filtering can be added externally. |
| TPS54560QDGQRQ1 | 3.5–60 V input, 5 V/5 A, 18 µA IQ, no LP mode, SOIC-10 | Higher VIN max and IOUT, but larger footprint and no wettable flank - less suitable for automated optical inspection. | Selected when 60 V transient immunity is mandatory and thermal pad solder joint inspection is not required. |
Compared with MPQ4423AGL-AEC1-P and TPS54560QDGQRQ1, the A81805KESJSR-1 delivers superior EMI performance via integrated dither, lower quiescent current for battery longevity, and wettable flank packaging for reliable automotive reflow yield - without sacrificing AEC-Q100 Grade 0 compliance.
Availability
A81805KESJSR-1 is available at Aetrix Electronics and suitable for automotive infotainment, ADAS camera modules, and industrial telematics trackers requiring stable component supply with AEC-Q100 qualification and long-term lifecycle support.
Supply support for A81805KESJSR-1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer of high-performance power ICs and magnetic sensors, specializing in automotive-grade motion control and energy-efficient power conversion solutions.
The A81805 product line targets demanding automotive and industrial DC-DC conversion needs - emphasizing ultra-low IQ, AEC-Q100 reliability, integrated EMI mitigation, and thermal robustness in compact QFN packages.
FAQ
What is the output voltage tolerance of the A81805KESJSR-1 over temperature?
The A81805KESJSR-1 delivers 5 V output with ±1.5% accuracy across the full −40°C to +150°C junction temperature range, verified per AEC-Q100 Grade 0 test conditions. This tight tolerance ensures reliable operation of downstream 5 V logic without additional post-regulation, even under extreme under-hood thermal cycling.
Does the A81805KESJSR-1 support synchronization to an external clock?
Yes, the A81805KESJSR-1 supports PLL-based synchronization via its SYNC pin, accepting external clocks from 400 kHz to 2.5 MHz. When synchronized, it maintains spread-spectrum dithering and remains in PWM mode - enabling deterministic EMI alignment across multiple regulators on the same PCB.
How does the A81805KESJSR-1 manage thermal performance in automotive environments?
The A81805KESJSR-1 uses a 4 mm × 4 mm wettable flank QFN with exposed thermal pad, achieving RθJC = 8°C/W and RθJA = 31°C/W on Allegro's evaluation board. Its thermal shutdown activates at 170°C with 20°C hysteresis, and LP mode disables TSD to preserve ultra-low IQ - balancing safety and efficiency.
Can the A81805KESJSR-1 start up into a pre-biased output?
Yes, the A81805KESJSR-1 supports pre-bias startup: it safely ramps the output from an existing 5 V rail without reverse current or output overshoot. This feature is validated for use in redundant power systems and hot-swap applications where output capacitance retains charge between power cycles.
What protection features are integrated into the A81805KESJSR-1?
The A81805KESJSR-1 integrates pulse-by-pulse current limit, hiccup-mode short-circuit protection, BOOT over/undervoltage detection, VIN undervoltage lockout (3.55 V turn-on), VOUT overvoltage (5.375 V) and undervoltage (4.625 V) protection, thermal shutdown at 170°C, and pin-fault diagnostics - meeting ASIL-B functional safety requirements for automotive subsystems.
A81805KESJSR-1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3.5V
- Voltage - Input (Max):
- 36V
- Voltage - Output (Min/Fixed):
- 5V
- Voltage - Output (Max):
- -
- Current - Output:
- 2.5A
- Frequency - Switching:
- 400kHz ~ 2.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 20-QFN (4x4)
A81805KESJSR-1 FAQ
1.How can I place an order for A81805KESJSR-1 through Aetrix?
Please submit a Request for Quotation (RFQ) for A81805KESJSR-1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A81805KESJSR-1 reliable?
The price and inventory of A81805KESJSR-1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A81805KESJSR-1 is usually 5 days.
3.What payment methods are accepted for A81805KESJSR-1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A81805KESJSR-1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A81805KESJSR-1?
A81805KESJSR-1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A81805KESJSR-1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A81805KESJSR-1?
For technical support, including A81805KESJSR-1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A81805KESJSR-1 requirements.
6.How does Aetrix verify that A81805KESJSR-1 is sourced from the original manufacturer or authorized distributors?
All A81805KESJSR-1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A81805KESJSR-1 meets industry standards.
7.What is the process for return or replacement of A81805KESJSR-1?
All A81805KESJSR-1 units undergo pre-shipment inspection (PSI). If there is an issue with A81805KESJSR-1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A81805KESJSR-1 part is unused and in its original packaging.
Return procedure for A81805KESJSR-1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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