My Inquiry
My Account
Allegro MicroSystems A8651KLPTR-T
- Part No.:
- A8651KLPTR-T
- Manufacturer:
- Allegro MicroSystems
- Package:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
A8651KLPTR-T.pdf
- Description:
- IC REG BUCK ADJ 2A DL 20TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,858
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
A8651KLPTR-T from Allegro MicroSystems is a dual-channel, synchronous step-down DC/DC regulator integrating high-side P-channel (80 mΩ) and low-side N-channel (55 mΩ) MOSFETs per channel, delivering up to 2 A per output from 2.5–5.5 V input down to 0.8 V output, with adjustable 350 kHz–2.2 MHz switching frequency and AEC-Q100 qualification for automotive power rails.
For engineers reviewing the A8651KLPTR-T datasheet, A8651KLPTR-T pinout, A8651KLPTR-T application, or A8651KLPTR-T equivalent, key selection criteria include dual independent EN/NPOR control, 7.5 ms NPOR delay, <5 µA sleep current, 180° phase shift between channels, and open-circuit/short-to-ground fault tolerance at every pin.
Technical Context
The A8651KLPTR-T implements current-mode PWM control with transconductance error amplifiers (750 µA/V typ), external compensation (RZ/CZ/CP), and slope compensation scaled to switching frequency. Each regulator features independent soft-start (externally set via SSx), pre-biased startup capability, and pulse-by-pulse OCP with adjustable current limit via ISETx resistors.
It supports synchronization to an external clock (1.2× to 1.5× fOSC) on the FSET/SYNC pin, enforces non-overlap timing (15 ns gate driver dead time), and provides dual 180°-phase-shifted outputs to reduce input ripple. Protection includes UVLO (2.25 V stop threshold), hiccup-mode short-circuit response, thermal shutdown (170 °C typ), and pin-level fault tolerance compliant with stringent automotive requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 2.5 V to 5.5 V - supports single-cell Li-ion, automotive battery rail (with UVLO stop at 2.25 V max). |
| Output current per channel | Up to 2 A - enables dual-core SoC or multi-rail audio subsystems without external MOSFETs. |
| Switching frequency | 0.35–2.2 MHz - adjustable via RFSET resistor; allows optimization of size (higher f) vs. efficiency (lower f). |
| Reference voltage | 800 mV ±1% - sets minimum output voltage; enables precise 0.8 V core supply with RFB divider. |
| NPOR delay | 7.5 ms (A8651 variant) - fixed active-low open-drain reset signal timing for sequenced power-up. |
| Sleep mode current | <5 µA - enables ultra-low quiescent operation in always-on automotive modules. |
| MOSFET RDS(on) | 80 mΩ (HS), 55 mΩ (LS) - integrated switches eliminate external FETs and reduce BOM count and layout area. |
Pinout & Package
Package: 20-pin TSSOP with exposed thermal pad (suffix LP), lead-free, 100% matte-tin plating, rated for –40°C to +125°C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 10 (SW1, SW2) | High-side MOSFET drain outputs | Connect directly to power inductors; require wide copper traces and minimal loop area for EMI control. |
| 2, 9 (PGND1, PGND2) | Power ground returns for each switcher | Must be tied to local ground planes under inductors; separate from signal GND to avoid noise coupling. |
| 3, 8 (EN1, EN2) | Independent enable inputs | Logic-high (>1.8 V) activates respective regulator; falling edge below 0.8 V disables within 10 µs. |
| 4, 7 (ISET1, ISET2) | Pulse-by-pulse current limit setting | Resistor to GND programs OCP threshold (e.g., 4.1 A at 5% duty cycle with 41.2 kΩ). |
| 5 (FSET/SYNC) | Oscillator frequency set / sync input | RFSET to GND sets base fOSC; AC-coupled external clock enables 1.2×–1.5× frequency boost. |
| 6, 15 (NPOR2, NPOR1) | Active-low open-drain reset outputs | Assert low for 7.5 ms after VOUTx reaches 92% of target; requires external pull-up for logic interface. |
| 11, 20 (VIN2, VIN1) | Power inputs for regulators | VIN1 powers all internal circuitry; must be present first. Both require local 10 µF ceramic capacitors. |
| 12, 19 (SS2, SS1) | Soft-start timing nodes | Capacitor to GND sets ramp time (e.g., 400 µs with 10 nF); also determines hiccup period during fault. |
| 13, 17 (COMP2, COMP1) | Error amplifier compensation outputs | Connect RZ–CZ–CP network here to stabilize current-mode loop; critical for transient response. |
| 14, 18 (FB2, FB1) | Feedback voltage inputs | Resistor divider from VOUTx sets regulation point; bias current ≤300 nA minimizes divider error. |
| 16 (GND) | Signal ground reference | Separate from PGND; connects to system ground plane and serves as reference for analog blocks. |
| PAD (exposed) | Thermal dissipation path | Must be soldered to PCB ground plane with ≥6 thermal vias to maintain TJ ≤150°C at full load. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent regulation | Two fully isolated 2 A buck channels with separate EN, NPOR, SS, COMP, and FB pins - enables asymmetric rail sequencing and fault isolation. |
| Automotive-grade fault tolerance | Open-circuit, adjacent-pin short, and short-to-ground protection on all pins - satisfies ASIL-B system-level requirements without external monitoring. |
| Phase-shifted dual output | 180° switching phase between SW1 and SW2 - reduces input capacitor RMS current by ~30%, lowering thermal stress and size. |
| Pre-biased startup support | Regulator ramps output from non-zero initial VOUT without reverse current - essential for hot-swap and multi-rail systems with staggered power-up. |
| Stable with ceramic output caps | No minimum ESR requirement - allows use of compact, low-ESR X7R/X5R MLCCs instead of bulk electrolytics, saving board space and improving reliability. |
Applications
| GPS/Infotainment Power | Automotive Audio Amplifier |
|---|---|
Use Scenario: Dual-rail power for GPS receiver (1.8 V) and infotainment MCU (1.1 V) in head unit with strict EMI limits. IC Role / Device Role / Timing Role: Primary dual-output buck regulator providing tightly regulated, phase-shifted supplies with synchronized switching to minimize conducted emissions. Use Value: Eliminates need for two discrete converters; 180° phase shift cuts input ripple by 30%, reducing required input capacitance and cost. | Use Scenario: Powering Class-D audio amplifier ICs requiring clean 12 V and 5 V rails in vehicle cabin audio system. IC Role / Device Role / Timing Role: High-current dual buck controller delivering 2 A per rail with independent enable sequencing and NPOR coordination. Use Value: Independent EN/NPOR pins allow controlled power-up order; hiccup-mode protection prevents latch-up during speaker short events. |
| Home Audio DSP Supply | Network Router PoE Interface |
Use Scenario: Low-noise 1.2 V and 3.3 V supplies for high-fidelity audio DSP and ADC/DAC in premium home theater receivers. IC Role / Device Role / Timing Role: Dual synchronous buck regulator with ceramic-cap stable loop and <5 µA sleep current for standby mode. Use Value: Pre-biased startup avoids output voltage reversal; soft-start programmability prevents inrush into sensitive analog circuitry. | Use Scenario: Secondary regulation stage converting midspan PoE 48 V down to 5 V/3.3 V for Ethernet PHY and controller in industrial router. IC Role / Device Role / Timing Role: Input-tolerant dual buck (2.5–5.5 V input) used post-isolation DC/DC stage with robust UVLO and thermal shutdown. Use Value: AEC-Q100 qualification ensures reliability in harsh environments; pin-level short-circuit tolerance protects against connector faults. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A8651KLPTR-T-1 | Identical architecture and pinout; differs only in NPOR delay (120 µs vs. 7.5 ms) and updated production lot traceability. | Preferred where faster power-on reset response is required (e.g., real-time control loops), not suitable for legacy 7.5 ms timing-critical designs. | Select A8651KLPTR-T-1 for new designs unless 7.5 ms NPOR is explicitly mandated by system firmware. |
| TPS65217C | Single-chip PMIC with dual 2 A bucks + LDOs + battery charger; no phase shift; fixed 2.2 MHz fSW; no FSET/SYNC pin. | Targets portable battery-powered systems; lacks AEC-Q100 rating and automotive fault tolerance features (e.g., pin short-to-ground). | Choose only for non-automotive, space-constrained applications needing integrated charging - not a functional replacement for A8651KLPTR-T. |
Compared with A8651KLPTR-T-1, the original A8651KLPTR-T provides longer NPOR assertion for legacy firmware compatibility, while the TPS65217C offers integration at the expense of automotive qualification, phase control, and pin-level fault resilience.
Availability
A8651KLPTR-T is available at Aetrix Electronics and suitable for GPS/infotainment systems, automotive audio amplifiers, and home audio DSP power supplies requiring stable component supply, AEC-Q100 compliance, and dual-channel synchronous buck functionality.
Supply support for A8651KLPTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based semiconductor company specializing in high-performance power ICs, magnetic sensors, and motor driver solutions for automotive and industrial markets.
The A8651 product line delivers dual-channel, high-current synchronous buck regulators designed specifically for demanding automotive power distribution - emphasizing fault resilience, thermal robustness, and precise sequencing in safety-critical ECUs.
FAQ
What is the NPOR delay specification for A8651KLPTR-T?
The A8651KLPTR-T provides a fixed 7.5 ms active-low NPOR delay (typical 7.5 ms, min 4.0 ms, max 11 ms) after VOUTx reaches 92% of its target voltage. This timing is inherent to the A8651 variant and differs from the A8651KLPTR-T-1's 120 µs delay. The NPOR signal remains asserted until both outputs meet regulation, ensuring reliable system reset sequencing in automotive applications.
Can A8651KLPTR-T operate with pre-biased outputs?
Yes, the A8651KLPTR-T supports pre-biased startup: it safely ramps output voltage from a non-zero initial condition without forcing reverse current into the output capacitor. This behavior is enabled by internal circuitry that monitors FBx and adjusts soft-start dynamics accordingly, making A8651KLPTR-T suitable for hot-swap and multi-rail systems where outputs may already be charged.
What is the maximum allowable switching frequency when synchronizing A8651KLPTR-T to an external clock?
The A8651KLPTR-T supports synchronization up to 2.5 MHz maximum, with valid SYNC frequency ranging from 1.2× to 1.5× the base fOSC set by RFSET. For example, with RFSET = 24.9 kΩ (fOSC ≈ 1.0 MHz), the external SYNC clock may be applied between 1.2 MHz and 1.5 MHz. Exceeding 2.5 MHz violates absolute maximum ratings and risks unstable operation.
How does the A8651KLPTR-T handle thermal overload conditions?
The A8651KLPTR-T incorporates thermal shutdown (TSD) with a typical activation threshold of 170°C and 20°C hysteresis. When junction temperature exceeds TSD(th), the device disables both regulators, pulls COMPx low via ~1.5 kΩ, and asserts NPOR. Recovery occurs only after temperature falls below (TSD(th) – TSD(HYS)), ensuring safe cooldown before restart - a critical feature for under-hood automotive deployment.
Is A8651KLPTR-T compatible with ceramic output capacitors only?
Yes, the A8651KLPTR-T is explicitly characterized and stabilized for use with low-ESR ceramic output capacitors (X7R/X5R MLCCs); no minimum ESR is required. Its current-mode control architecture and transconductance error amplifier (750 µA/V typ) ensure stability across the full ceramic capacitance range, eliminating the need for bulky, less-reliable electrolytic or tantalum capacitors in space-constrained automotive modules.
A8651KLPTR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 2A
- Frequency - Switching:
- 350kHz ~ 2.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP-EP
A8651KLPTR-T FAQ
1.How can I place an order for A8651KLPTR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A8651KLPTR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A8651KLPTR-T reliable?
The price and inventory of A8651KLPTR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A8651KLPTR-T is usually 5 days.
3.What payment methods are accepted for A8651KLPTR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A8651KLPTR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A8651KLPTR-T?
A8651KLPTR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A8651KLPTR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A8651KLPTR-T?
For technical support, including A8651KLPTR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A8651KLPTR-T requirements.
6.How does Aetrix verify that A8651KLPTR-T is sourced from the original manufacturer or authorized distributors?
All A8651KLPTR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A8651KLPTR-T meets industry standards.
7.What is the process for return or replacement of A8651KLPTR-T?
All A8651KLPTR-T units undergo pre-shipment inspection (PSI). If there is an issue with A8651KLPTR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A8651KLPTR-T part is unused and in its original packaging.
Return procedure for A8651KLPTR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
A8651KLPTR-T Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
