Allegro MicroSystems A8904SLP-T
- Part No.:
- A8904SLP-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
A8904SLP-T.pdf
- Description:
- IC MOTOR DRVR 4.5V-5.5V 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,907
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
A8904SLP-T from Allegro MicroSystems is a 3-phase brushless DC motor controller/driver with integrated back-EMF sensing, linear current-mode speed regulation, and programmable serial interface. It delivers up to 1.2 A per phase via low-RDS(on) N-channel DMOS half-bridges, supports sensorless commutation, and operates with 4–14 V load supply and 4.5–5.5 V logic supply. Used in precision spindle control for optical drives and industrial fans requiring stable high-speed rotation.
For engineers reviewing the A8904SLP-T datasheet, A8904SLP-T pinout, A8904SLP-T application, or A8904SLP-T equivalent, key selection criteria include programmable transconductance gain (250/500 mA/V), adaptive commutation delay timing, thermal shutdown at 165°C, and compatibility with external tachometer inputs for high-accuracy speed lock.
Technical Context
The A8904SLP-T implements a six-state sequencer for sensorless commutation, using FCOM toggling on back-EMF zero crossings at the centertap to trigger state transitions. Its adaptive commutation delay circuit dynamically adjusts timing via CD1/CD2 capacitor discharge to compensate for winding inductance.
Speed regulation uses a frequency-locked loop (FLL) comparing internal TACH (derived from FCOM) or external SECTOR DATA against a 14-bit REF counter clocked by an oscillator up to 20 MHz. Linear current control is applied through the FILTER terminal voltage, scaled by transconductance gain and RS sense resistor (200 mΩ).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Output Current | 1.2 A per phase - sets continuous drive capability for mid-power BLDC motors |
| rDS(on) (Total) | 1.0 Ω typical - determines conduction loss and thermal rise under load |
| Load Supply Range | 4.0–14 V - supports 5 V and 12 V motor rails without external regulators |
| Transconductance Gain | 250 or 500 mA/V - selectable via D28 to scale current response to FILTER voltage |
| FLL Oscillator Max | 20 MHz - defines maximum resolution and update rate for speed reference counter |
| Thermal Shutdown | 165°C with 20°C hysteresis - enables self-protection during overload or poor heatsinking |
| Serial Clock Max | 3.3 MHz - sets programming bandwidth for real-time configuration of speed, direction, diagnostics |
Pinout & Package
The A8904SLP-T is housed in a 28-pin thin-profile TSSOP (Package LP) with exposed thermal pad, lead-free construction, and 100% matte tin plating. Thermal resistance is 28°C/W (4-layer JEDEC PCB), enabling higher power density than the SOICW variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OUTA / OUTB / OUTC | Half-bridge power outputs | Drive motor phases A/B/C; each capable of ±1.4 A continuous, ±3.0 A peak braking |
| LOAD SUPPLY (VBB) | Motor supply input | Accepts 4–14 V; powers DMOS drivers and internal charge pump for high-side gate drive |
| LOGIC SUPPLY (VDD) | Digital core supply | 5 V ±10%; UVLO triggers at 3.6 V (falling) / 3.9 V (rising) to prevent erratic operation |
| FILTER | Speed control integrator node | Voltage here linearly controls low-side current; externally filtered to shape closed-loop response |
| SECTOR DATA | External tachometer input | Accepts index/sector pulses for precise speed lock independent of back-EMF quality |
| BRAKE | Active-low dynamic brake enable | Shorts all three windings to ground; also controllable via serial port bit D1 |
| DATA OUT | Multiplexed diagnostic output | Selectable via D22/D23: TACH, SYNC, FCOM, or thermal shutdown flag (HIGH = fault) |
| CST / CD1 / CD2 / CWD | Timing capacitors | Set start-up oscillator period, commutation delay, and blanking/watchdog timing respectively |
| CENTERTAP | Back-EMF reference point | Connects to motor Y-centertap; used as comparator reference for zero-crossing detection |
| GROUND (Pins 1, 8, 22) | Power/analog/digital return | Must be connected together externally per LP package note; serves as thermal sink |
Key Features
| Feature | Design Value |
|---|---|
| Sensorless commutation | Self-contained six-state sequencer using FCOM toggling on centertap-referenced back-EMF zero crossings |
| Programmable current limit | Eight selectable levels (125–1400 mA) via D3/D4/D28 bits, scaled to transconductance gain |
| Adaptive commutation delay | CD1/CD2 capacitor discharge triggered by FCOM edges compensates for inductive lag in real time |
| YANK speed loop initialization | Pulls FILTER to VFILTERTH at startup to force max current until first ERROR FAST signal releases it |
| Real-time diagnostics | DATA OUT multiplexer provides live TACH, SYNC, FCOM, or thermal shutdown status without halting operation |
Applications
| Optical Disk Drive Spindle Control | Industrial Fan Speed Regulation |
|---|---|
Use Scenario: Maintaining constant 5400–15,000 RPM across varying disc mass and bearing wear in CD/DVD/Blu-ray drives. IC Role / Device Role / Timing Role: Sensorless BLDC controller generating commutation timing from back-EMF zero crossings and regulating speed via FLL against internal REF counter. Use Value: Eliminates Hall sensors and reduces BOM cost while achieving <±0.5% speed stability over temperature and voltage variation. | Use Scenario: Variable-speed cooling for PLC cabinets and power converters where acoustic noise and efficiency are critical. IC Role / Device Role / Timing Role: Motor driver with external SECTOR DATA input accepting encoder pulses for closed-loop speed lock under variable airflow load. Use Value: Enables precise 100–3000 RPM control with <1% error using low-cost optical encoder feedback instead of complex current sensing. |
| Medical Pump Rotor Control | Automotive HVAC Blower |
Use Scenario: Silent, jitter-free rotation of peristaltic pump rollers in infusion devices requiring smooth flow and no torque ripple. IC Role / Device Role / Timing Role: Linear current-mode controller using FILTER voltage to directly modulate low-side MOSFET conduction for ripple-free torque. Use Value: Delivers <0.1% speed ripple and <20 dB lower EMI vs. PWM-based drivers due to analog current regulation. | Use Scenario: High-reliability cabin air blower operating across -40°C to +105°C ambient with reverse-polarity and load-dump protection. IC Role / Device Role / Timing Role: Integrated motor controller with thermal shutdown (165°C), undervoltage lockout (3.6 V), and programmable watchdog timer for fail-safe operation. Use Value: Meets AEC-Q100 stress requirements via robust BCD process and eliminates need for external protection ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-phase BLDC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A8902CLBA-T | Pin-for-pin compatible; lacks serial port programmability, fixed transconductance (500 mA/V), no external tach input | Targeted for cost-sensitive, fixed-parameter designs without need for runtime reconfiguration | Select when serial interface, gain flexibility, or SECTOR DATA support are unnecessary |
| DRV10983ZRTVT | Integrated gate drivers only; requires external MCU for commutation logic and FLL; no back-EMF sensing circuitry | Used in systems with existing host processor handling sensorless algorithms and speed control | Select when full system-level control resides in firmware and discrete power stage integration is preferred |
Compared with A8904SLP-T, A8902CLBA-T offers hardware simplicity but sacrifices configurability, while DRV10983ZRTVT shifts intelligence to the host MCU-making A8904SLP-T optimal for standalone, self-contained motor control where minimal external components and real-time diagnostics are required.
Availability
A8904SLP-T is available at Aetrix Electronics and suitable for optical drive spindle control, industrial fan regulation, medical pump actuation, and automotive HVAC blower applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for A8904SLP-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer of high-performance magnetic sensors and power ICs, founded in 1989 and headquartered in Worcester, Massachusetts.
The A8904 product line targets sensorless BLDC motor control in space-constrained, thermally demanding applications-leveraging Allegro's BCD process to integrate bipolar analog, CMOS logic, and DMOS power devices on a single die.
FAQ
What is the package type and thermal performance of the A8904SLP-T?
The A8904SLP-T uses a 28-pin TSSOP package (LP) with exposed thermal pad and lead-free matte tin plating. Its thermal resistance is 28°C/W on a 4-layer JEDEC-standard PCB, significantly lower than the 35°C/W of the SOICW variant-enabling higher continuous current in compact layouts. The exposed pad must be soldered to a thermal plane for optimal performance.
How does the A8904SLP-T achieve sensorless commutation without Hall sensors?
The A8904SLP-T senses back-EMF zero crossings at the motor centertap using internal comparators. During each six-state commutation cycle, one phase is left floating (high-impedance), and its voltage is compared to the centertap. When they match, the FCOM signal toggles-triggering the adaptive delay circuit to advance to the next state. This eliminates external position sensors while maintaining synchronization across speed ranges.
Can the A8904SLP-T operate with an external tachometer signal instead of internal back-EMF sensing?
Yes-the A8904SLP-T accepts external sector or index pulses on the SECTOR DATA pin. Setting serial port bit D19 = 1 enables this mode, allowing the FLL to lock to the external tach signal instead of internally generated FCOM. This improves speed accuracy in noisy environments or with motors exhibiting weak back-EMF, and is commonly used in optical drive applications with dedicated servo tracks.
What are the key timing capacitors in the A8904SLP-T and how are they selected?
The A8904SLP-T uses four critical timing capacitors: CST (start-up oscillator), CD1/CD2 (commutation delay), and CWD (blanking/watchdog). CST sets initial spin-up timing; CD1/CD2 values determine commutation advance based on motor pole count and speed; CWD duration must exceed diode recirculation time during state transitions. Values are calculated using manufacturer-provided formulas involving programmed charge currents and threshold voltages.
Does the A8904SLP-T support dynamic braking, and how is it activated?
Yes-the A8904SLP-T supports dynamic braking via two methods: (1) pulling the BRAKE pin low, which activates all three sink drivers to short motor windings to ground; or (2) setting serial port bit D1 = 1. Both methods deliver ±3.0 A peak braking current for ≤800 ms before decaying to ±1.4 A. An external RC network on BRAKE sets delay timing, preventing unintended activation during commutation transients.
A8904SLP-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushless DC (BLDC)
- Function:
- Controller - Commutation, Direction Management
- Output Configuration:
- Pre-Driver - Half Bridge (3)
- Interface:
- SPI
- Technology:
- CMOS, DMOS
- Step Resolution:
- -
- Applications:
- General Purpose
- Current - Output:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Voltage - Load:
- 4V ~ 14V
- Operating Temperature:
- -20°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP-EP
A8904SLP-T FAQ
1.How can I place an order for A8904SLP-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A8904SLP-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A8904SLP-T reliable?
The price and inventory of A8904SLP-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A8904SLP-T is usually 5 days.
3.What payment methods are accepted for A8904SLP-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A8904SLP-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A8904SLP-T?
A8904SLP-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A8904SLP-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A8904SLP-T?
For technical support, including A8904SLP-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A8904SLP-T requirements.
6.How does Aetrix verify that A8904SLP-T is sourced from the original manufacturer or authorized distributors?
All A8904SLP-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A8904SLP-T meets industry standards.
7.What is the process for return or replacement of A8904SLP-T?
All A8904SLP-T units undergo pre-shipment inspection (PSI). If there is an issue with A8904SLP-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A8904SLP-T part is unused and in its original packaging.
Return procedure for A8904SLP-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
A8904SLP-T Tags
-
DRV2603RUNR
Texas Instruments

-
DRV8837CDSGR
Texas Instruments

-
DRV8837DSGR
Texas Instruments

-
DRV8838DSGR
Texas Instruments

-
DRV8839DSSR
Texas Instruments

-
EMC2301-1-ACZL-TR
Microchip Technology

-
DRV8231ADSGR
Texas Instruments

-
EMC2302-2-AIZL-TR
Microchip Technology

-
DRV8800PWPR
Texas Instruments

-
DRV8835DSSR
Texas Instruments

-
EMC2303-1-KP-TR
Microchip Technology

-
DRV8876PWPR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

