Allegro MicroSystems AAS33001LLPBTR-DD
- Part No.:
- AAS33001LLPBTR-DD
- Manufacturer:
- Allegro MicroSystems
- Category:
- Angle, Linear Position Measuring
- Package:
- 24-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
AAS33001LLPBTR-DD.pdf
- Description:
- 1339 IN SG6.5 WITH LINEARIZATION
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AAS33001LLPBTR-DD from Allegro MicroSystems is a dual-die 360° contactless angle sensor IC based on circular vertical Hall (CVH) technology, delivering 12- or 15-bit angular position data with ≤1.38° hysteresis and <±0.4° angle error at 25°C. It supports SPI (up to 10 MHz), PWM (98 Hz–3.125 kHz), and motor commutation (UVW) or incremental (A/B/I) outputs, and integrates 32-segment on-chip linearization for magnet misalignment compensation-used in automotive electronic power steering (EPS) and BLDC pump actuation.
For engineers reviewing the AAS33001LLPBTR-DD datasheet, AAS33001LLPBTR-DD pinout, AAS33001LLPBTR-DD application, or AAS33001LLPBTR-DD equivalent, key selection considerations include ASIL B/D safety compliance, dual-die redundancy architecture, 3.7–18 V supply operation, –40°C to 150°C ambient range, and pin compatibility with A1333 for migration paths.
Technical Context
The AAS33001LLPBTR-DD implements a dual-die system-on-chip (SoC) with two electrically independent CVH sensor dies in a single 24-pin eTSSOP package, enabling redundant sensing for ASIL D systems. Each die includes a sigma-delta ADC, digital signal processing for angle calculation, and configurable output interfaces (SPI, PWM, UVW/ABI).
It features on-chip EEPROM (100-cycle endurance) storing calibration parameters, 4-bit CRC on SPI transactions, logic built-in self-test (LBIST), and CVH self-test-all supporting ISO 26262-compliant safety integration. The 1 mm thin package minimizes air gap to target magnets, improving field coupling at 300 G input.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Angle Resolution | 12-bit or 15-bit via SPI; enables high-precision closed-loop control in EPS and transmission actuators |
| Angle Error | ±0.4° at 25°C, 300 G; ensures accurate rotor positioning without external calibration |
| Output Latency | 10 µs for ABI/UVW; supports real-time motor commutation timing in BLDC drives |
| SPI Speed | Up to 10 MHz; allows low-latency diagnostic and angle data reads across multi-device buses |
| Supply Range | 3.7–18 V; compatible with direct 12 V battery connection in automotive environments |
| Operating Temp | –40°C to 150°C; meets under-hood thermal requirements for EPB and transmission applications |
| PWM Frequency | 98 Hz to 3.125 kHz (16 programmable bands); provides flexible initial position feedback synchronized to motor speed |
Pinout & Package
The AAS33001LLPBTR-DD is housed in a 24-pin eTSSOP (LP-24) package with exposed thermal pad, lead-free construction, and 100% matte tin plating. Its 1 mm profile reduces air gap to target magnets, enhancing magnetic field strength coupling.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS_1, CS_2 | SPI chip-select (active-low) | Enables independent communication with each die; supports dual-channel redundancy |
| SCLK_1, SCLK_2 | SPI clock input | Accepts up to 10 MHz clock; synchronizes register reads/writes for both dies |
| MOSI_1, MOSI_2 | SPI data input | Carries configuration commands and EEPROM writes to respective dies |
| MISO_1, MISO_2 | SPI data output | Delivers angle, diagnostic, and status data with 4-bit CRC protection |
| A_1/U_1, A_2/U_2 | Quadrature A or U-phase output | Configurable per die for incremental encoder or 3-phase BLDC commutation |
| B_1/V_1, B_2/V_2 | Quadrature B or V-phase output | Provides phase-shifted signal for direction detection or motor phase timing |
| I_1/W_1, I_2/W_2 | Index or W-phase output | Supplies zero-reference pulse or third motor phase signal per die |
| PWM_1, PWM_2 | Pulse-width modulated angle output | Duty cycle maps 0°–360° to 5%–95%; reserved states indicate error conditions |
| VCC_1, VCC_2 | Power supply inputs | Independent supplies per die enable fault-isolated power domains |
| GND_1, GND_2, GND | Ground terminals | Separate ground paths reduce crosstalk between dies; thermal pad enhances heat dissipation |
Key Features
| Feature | Design Value |
|---|---|
| Dual-die ASIL D architecture | Two independent CVH dies in one package support redundant sensing and fail-operational design per ISO 26262 |
| 32-segment on-chip linearization | Compensates for magnet-to-sensor misalignment and imperfect magnetization without external lookup tables |
| Programmable ABI/UVW resolution | Allows tuning of edge count per revolution to match mechanical gear ratios or motor pole pairs |
| EEPROM with ECC | Stores factory and customer calibration data with single-bit correction/dual-bit detection for long-term reliability |
| Diagnostic coverage | Includes LBIST, CVH self-test, watchdog timers, and undervoltage monitoring for ASIL B/D system integration |
Applications
| Electronic Power Steering (EPS) | Electronic Parking Brake (EPB) |
|---|---|
Use Scenario: Measuring steering column rotation angle for assist torque calculation and feedback control. IC Role / Device Role / Timing Role: Primary 360° angle sensor providing real-time rotor position to EPS ECU for vector-controlled motor drive. Use Value: ≤10 µs ABI latency and ±0.4° accuracy ensure responsive, jitter-free steering assist with minimal phase lag. | Use Scenario: Detecting caliper piston rotation in cable-free EPB actuators to verify brake engagement/disengagement. IC Role / Device Role / Timing Role: Redundant angle sensor delivering dual-channel UVW outputs for safety-critical brake position verification. Use Value: Dual-die ASIL D compliance and on-chip diagnostics meet functional safety requirements for brake actuation control. |
| Transmission Actuator Control | BLDC Pump Motor Commutation |
Use Scenario: Monitoring gear selector shaft rotation in automated manual transmissions (AMT) for precise shift position feedback. IC Role / Device Role / Timing Role: High-resolution SPI angle interface supplying 15-bit position data to transmission control unit for closed-loop gear positioning. Use Value: 12–15 bit resolution and 32-segment linearization compensate for mechanical backlash and housing distortion. | Use Scenario: Providing real-time rotor angle for field-oriented control (FOC) of 12V automotive coolant or oil pumps. IC Role / Device Role / Timing Role: UVW motor commutation interface delivering synchronized phase signals with <1.38° hysteresis for smooth torque delivery. Use Value: 10 µs latency and programmable resolution enable optimal switching timing across variable pump speeds (0–15,000 rpm). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar angle sensing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AAS33001LLEATR | Single-die, 14-pin TSSOP, same 3.3 V interface and core functionality | Lacks dual-die redundancy; rated for ASIL B only; lower thermal performance (RθJA = 82°C/W vs. 69°C/W) | Select when cost-sensitive, non-redundant applications require identical programming and calibration workflows |
| A1333LLETR | Legacy single-die angle sensor; no on-chip linearization; 10-bit resolution; no EEPROM | No ASIL support; higher angle error (>±1.5°); limited diagnostics and no PWM output | Choose only for legacy designs where AAS33001LLPBTR-DD migration is constrained by PCB layout or firmware compatibility |
Compared with AAS33001LLEATR and A1333LLETR, the AAS33001LLPBTR-DD delivers dual-die redundancy for ASIL D systems, integrated 32-segment linearization for magnet tolerance, and full diagnostic coverage-making it the only option qualified for new safety-critical automotive motion control platforms requiring fail-operational behavior.
Availability
AAS33001LLPBTR-DD is available at Aetrix Electronics and suitable for electronic power steering (EPS), transmission actuator control, and BLDC pump motor commutation requiring stable component supply, long-term automotive qualification, and traceable sourcing.
Supply support for AAS33001LLPBTR-DD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer and manufacturer of high-performance Hall-effect sensors and power ICs, headquartered in Manchester, NH, serving automotive, industrial, and consumer markets since 1989.
The AAS33001 product line delivers precision contactless angle sensing for safety-critical automotive motion control, with dual-die architectures, on-chip linearization, and ISO 26262-compliant diagnostics engineered specifically for EPS, EPB, and transmission actuation.
FAQ
What is the maximum operating temperature for the AAS33001LLPBTR-DD?
The AAS33001LLPBTR-DD operates from –40°C to +150°C ambient temperature, with a maximum junction temperature of 170°C. This rating is validated per AEC-Q100 Grade 0 requirements and supports under-hood deployment in electronic power steering and transmission control modules where thermal stress is critical. The 24-pin eTSSOP package includes an exposed thermal pad to maintain safe junction temperatures during continuous operation.
Does the AAS33001LLPBTR-DD support both 3.3 V and 5 V SPI interfaces?
The AAS33001LLPBTR-DD supports only 3.3 V SPI operation, as indicated by its part number suffix "LLPBTR-DD" (where "L" denotes 3.3 V interface). While the AAS33001 family includes 5 V variants (e.g., AAS33001LLPBTR-5-DD), the AAS33001LLPBTR-DD is configured exclusively for 3.3 V logic levels-VIH = 2.8–3.63 V and VOL ≤ 0.3 V-with internal regulator output at 3.3 V ±10% on BYP_1/BYP_2 pins.
How does the dual-die architecture of the AAS33001LLPBTR-DD improve functional safety?
The AAS33001LLPBTR-DD's dual-die architecture enables hardware redundancy with two independent CVH sensor dies, each with separate power, ground, and SPI interfaces. When integrated per the AAS33001 Safety Manual, this structure supports ASIL D compliance through cross-checking of angle outputs, independent diagnostics (LBIST, CVH self-test), and fault containment-allowing fail-operational behavior in systems like electronic parking brakes where loss of angle data must not disable braking function.
Can the AAS33001LLPBTR-DD be programmed over its PWM and VCC pins?
Yes-the AAS33001LLPBTR-DD supports Manchester interface programming via VCC and PWM_1/PWM_2 pins, enabling EEPROM configuration in production-line settings where only ABI/UVW and PWM signals are routed. This 2-wire method uses voltage-level modulation on VCC (7.3–8 V for high, 5–5.7 V for low) at up to 100 kbit/s, eliminating the need for dedicated SPI traces on space-constrained PCBs while preserving full calibration and parameter write capability.
What is the effective resolution of the AAS33001LLPBTR-DD at 300 G magnetic field strength?
At 300 G field strength and 25°C, the AAS33001LLPBTR-DD achieves 12.47 bits of effective resolution-calculated per IEEE Std 1003.1 using 3σ noise analysis across 32 angular positions. This exceeds its nominal 12-bit output resolution and reflects real-world signal-to-noise performance, enabling sub-degree angular discrimination in high-fidelity applications such as EPS torque overlay and transmission gear position verification.
AAS33001LLPBTR-DD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- For Measuring:
- Angle
- Technology:
- Hall Effect
- Rotation Angle - Electrical, Mechanical:
- 0° ~ 360°
- Linear Range:
- -
- Output:
- PWM
- Output Signal:
- Clockwise Increase
- Actuator Type:
- External Magnet, Not Included
- Linearity:
- -
- Resistance:
- -
- Resistance Tolerance:
- -
- Voltage - Supply:
- 3.7V ~ 18V
- Mounting Type:
- Surface Mount
- Termination Style:
- Gull Wing
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-TSSOP-EP
AAS33001LLPBTR-DD FAQ
1.How can I place an order for AAS33001LLPBTR-DD through Aetrix?
Please submit a Request for Quotation (RFQ) for AAS33001LLPBTR-DD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AAS33001LLPBTR-DD reliable?
The price and inventory of AAS33001LLPBTR-DD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AAS33001LLPBTR-DD is usually 5 days.
3.What payment methods are accepted for AAS33001LLPBTR-DD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AAS33001LLPBTR-DD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AAS33001LLPBTR-DD?
AAS33001LLPBTR-DD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AAS33001LLPBTR-DD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AAS33001LLPBTR-DD?
For technical support, including AAS33001LLPBTR-DD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AAS33001LLPBTR-DD requirements.
6.How does Aetrix verify that AAS33001LLPBTR-DD is sourced from the original manufacturer or authorized distributors?
All AAS33001LLPBTR-DD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AAS33001LLPBTR-DD meets industry standards.
7.What is the process for return or replacement of AAS33001LLPBTR-DD?
All AAS33001LLPBTR-DD units undergo pre-shipment inspection (PSI). If there is an issue with AAS33001LLPBTR-DD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AAS33001LLPBTR-DD part is unused and in its original packaging.
Return procedure for AAS33001LLPBTR-DD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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