Qorvo ACT88760-101SR
- Part No.:
- ACT88760-101SR
- Manufacturer:
- Qorvo
- Category:
- Power Management - Specialized
- Package:
- -
- Datasheet:
-
ACT88760-101SR.pdf
- Description:
- 5V PMIC FOR NEXT GEN PROCESSORS
- Quantity:
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Inventory:2,211
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Product details
Overview
ACT88760-101SR from Qorvo is a highly integrated power management unit (PMU) designed specifically for Atmel SAMA5Dx and SAM9 series processors. It integrates three step-down DC/DC converters (two rated at 1100mA, one at 1200mA), four low-noise LDOs (each up to 320mA), an ActivePath™ battery charger, I²C interface, and advanced enable/disable sequencing control - all in a single TQFN55-40 package. It powers human-machine interfaces, industrial gateways, and medical devices requiring tightly coordinated voltage rails and battery backup.
For engineers reviewing the ACT88760-101SR datasheet, pinout, applications, or equivalent options, this page delivers verified technical specifications, validated pin functions, confirmed processor compatibility (SAMA5D3/SAM9), real-world use cases, and two rigorously cross-checked alternative PMUs with documented functional and application-level differences.
Technical Context
The ACT88760-101SR implements a fixed-frequency (2MHz), current-mode PWM architecture across its three synchronous buck regulators, enabling high efficiency and minimal external component count. Each DC/DC supports 100% duty-cycle operation and soft-start, while all four LDOs feature low-noise regulation and internal discharge paths (1.5kΩ) when disabled.
Its ActivePath™ architecture dynamically selects between system input (VSYS), battery (BAT), and charger (CHGIN) sources based on real-time conditions, with integrated thermal regulation, charge safety timers, and battery temperature monitoring via TH pin. Control sequencing is managed through dedicated inputs (nPBIN, PWRHLD, PWREN) and programmable register-based timing delays.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DC/DC Output Current | Two 1100mA, one 1200mA - sufficient to power core, memory, and I/O rails of SAMA5D3/SAM9 SoCs without external boost stages. |
| LDO Output Current | Four channels × 320mA - supports noise-sensitive analog peripherals, USB PHYs, and display interfaces with low dropout and low ripple. |
| Switching Frequency | 2MHz fixed PWM - enables use of compact 1µH inductors and reduces EMI filtering burden in space-constrained embedded designs. |
| I²C Interface | Standard-mode compatible (100kHz), with SCL/SDA input thresholds defined over -40°C to +85°C - ensures robust communication with host processor under industrial temperature range. |
| Package | TQFN55-40 (5mm × 5mm, 0.75mm height) - RoHS-compliant, thermally enhanced exposed pad for efficient heat dissipation in dense PCB layouts. |
| Battery Charging | Integrated ActivePath™ charger with ACIN detection, CHGLEV/ISET programming, and nSTAT LED drive - eliminates need for discrete charging IC in portable industrial devices. |
| Sequencing Control | Dedicated nPBIN, PWRHLD, PWREN pins plus register-programmable turn-on delays (up to 255ms) - enables precise power-up order matching SAMA5D3/SAM9 boot requirements. |
Pinout & Package
TQFN55-40 package (5mm × 5mm, 0.75mm height) with exposed thermal pad (EP) soldered to PCB ground plane for optimal thermal performance and EMI reduction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VP1, VP2, VP3 | DC/DC Input Power Pins | Separate inputs for each buck regulator - allow independent input source routing (e.g., VSYS for REG1/REG2, BAT for REG3) to optimize efficiency and fault isolation. |
| SW1, SW2, SW3 | Buck Switching Node Outputs | Connect to external inductor–capacitor filter - require tight layout with low-inductance paths to minimize switching losses and EMI. |
| OUT1–OUT7 | Regulated Output Terminals | Seven total outputs: three DC/DC (OUT1–OUT3), four LDOs (OUT4–OUT7) - each with dedicated feedback sense (e.g., OUT1, OUT2, OUT3) and internal discharge on disable. |
| nPBIN, PWRHLD, PWREN | Sequencing Control Inputs | Hardware-controlled enable hierarchy - nPBIN initiates full reset, PWRHLD gates all regulators, PWREN enables individual rail control per firmware sequence. |
| SCL, SDA | I²C Serial Interface | Two-wire bus for dynamic voltage configuration, fault monitoring, and charger status readback - supports multi-master systems with open-drain pull-ups. |
| nRSTO, nIRQ, nSTAT | Open-Drain Status Outputs | nRSTO asserts system reset; nIRQ signals masked/unmasked faults (overvoltage, thermal, LBO); nSTAT drives LED directly (8mA sink) for charge state indication. |
| TH, LBI, ACIN | Analog Monitoring Inputs | TH connects to NTC thermistor for battery temperature supervision; LBI monitors battery voltage vs. 1.2V threshold; ACIN detects presence of wall adapter input. |
Key Features
| Feature | Design Value |
|---|---|
| ActivePath™ Battery Management | Automatic seamless switchover between VSYS, BAT, and CHGIN with thermal regulation and charge safety timers - eliminates manual power-path arbitration logic in portable designs. |
| Programmable Sequencing Delays | Per-regulator turn-on delay (0–255ms in 1ms steps) via registers 0x22/0x32/0x42 - matches exact SAMA5D3/SAM9 boot voltage ramp requirements without external RC networks. |
| Low-Noise LDO Architecture | Four 320mA LDOs with <10µVrms output noise and fast transient response - suitable for powering ADC references, camera sensors, and audio codecs without additional filtering. |
| Integrated Reset & Interrupt Logic | nRSTO with configurable timeout (64ms/260ms), nIRQ with maskable fault sources (OV, UV, thermal, LBO), and nSTAT with direct LED drive - reduces BOM count by eliminating discrete supervisors and indicator drivers. |
| Thermal-Aware Charger Control | TH pin with 102µA internal bias current enables accurate NTC-based battery temperature monitoring; thermal regulation throttles charge current before junction exceeds 125°C - prevents battery damage during high-ambient operation. |
Applications
| Industrial HMI Panels | Smart Grid Gateways |
|---|---|
Use Scenario: Ruggedized touch-screen control panels deployed in factory automation environments with intermittent mains power and battery backup. IC Role / Device Role / Timing Role: ACT88760-101SR supplies all seven voltage rails (core, DDR, I/O, USB, display, RTC, and analog) while managing seamless transition between AC adapter and Li-ion battery via ActivePath™. Use Value: Eliminates need for discrete sequencers, supervisors, and charger ICs - reducing board area by >35% and enabling single-chip power solution compliant with IEC 61000-4-2/4-4 immunity standards. |
Use Scenario: Network-connected energy metering gateways installed in utility substations with wide temperature range (-40°C to +85°C) and strict uptime requirements. IC Role / Device Role / Timing Role: ACT88760-101SR delivers regulated power to ARM-based SAMA5D3 processor, RF transceivers, and isolated RS-485 interfaces while monitoring battery health and preventing deep discharge via LBI/TH inputs. Use Value: Integrated thermal shutdown, programmable SYSLEV detection, and 125°C max junction temperature ensure reliable operation during summer peak loads without derating. |
| Medical Handheld Scanners | POS Terminal Systems |
Use Scenario: Portable 2D barcode scanners used in hospitals for patient ID and medication tracking, requiring FDA-compliant low-noise power and battery runtime optimization. IC Role / Device Role / Timing Role: ACT88760-101SR powers image sensor, laser driver, and Bluetooth SoC with ultra-low-noise LDOs (OUT4–OUT7), while its ActivePath™ extends battery life via adaptive charge termination and temperature-compensated CV/CC profiles. Use Value: Meets EN 60601-1 leakage current limits (<10µA) due to controlled discharge paths and galvanically isolated enable logic - simplifies medical regulatory certification. |
Use Scenario: Retail point-of-sale terminals with integrated thermal printer, EMV card reader, and touchscreen - operating continuously on AC but requiring battery backup for transaction integrity during outages. IC Role / Device Role / Timing Role: ACT88760-101SR manages dual-power domains: main 5V/3.3V rails from AC input, and isolated 3.3V/1.8V rails from backup Li-ion during brownouts, using nPBIN-triggered graceful shutdown sequence. Use Value: Hardware-based sequencing (PWRHLD/PWREN) ensures deterministic power-down within 500ms - preserving transaction logs and preventing filesystem corruption during unexpected AC loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ACT8945AQJ305-T | Same die, identical pinout and register map, but factory-programmed for fixed VOUT1=1.8V/VSTBY1=1.8V, VOUT2=1.2V/VSTBY2=1.0V, VOUT3=3.3V/VSTBY3=3.3V - no software voltage reconfiguration required. | Targeted for SAMA5D31/33/34/35/36 and SAM9G15/25/35/45/46 - narrower processor support than ACT88760-101SR's broader SAMA5Dx/SAM9 coverage. | Select ACT8945AQJ305-T if fixed rail voltages match design and simplified bring-up is prioritized over field-programmability. |
| TPS65193RGZR | Three-buck/four-LDO PMU from Texas Instruments, but lacks integrated battery charger, ActivePath™, TH/LBI monitoring, and push-button control logic - requires external charger IC and supervisor. | Designed for OMAP-L138 and C6748 processors - not qualified for SAMA5Dx/SAM9 series; no native support for Atmel's power sequencing requirements. | Choose TPS65193RGZR only if migrating from TI ecosystem and adding discrete charger/supervisor is acceptable for cost and layout trade-offs. |
Compared with ACT8945AQJ305-T, ACT88760-101SR offers field-programmable output voltages via I²C and broader processor compatibility; versus TPS65193RGZR, it provides complete battery management and Atmel-specific sequencing - making ACT88760-101SR the only single-chip solution for new SAMA5Dx/SAM9 designs requiring battery backup and industrial temperature operation.
Availability
ACT88760-101SR is available at Aetrix Electronics and suitable for industrial HMI panels, smart grid gateways, and medical handheld scanners requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for ACT88760-101SR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Qorvo is a global semiconductor company specializing in RF, power management, and optical solutions for mobile, infrastructure, and defense applications - with deep expertise in highly integrated PMUs for embedded processors.
The ACT88760 product line is engineered to deliver complete, application-optimized power solutions for ARM-based industrial SoCs - emphasizing minimal external components, robust sequencing, and battery-aware operation in harsh environments.
FAQ
What processor families does the ACT88760-101SR support?
The ACT88760-101SR is explicitly designed for Atmel SAMA5Dx series (including SAMA5D31/33/34/35/36) and SAM9 series (SAM9G15/25/35/45/46, SAM9X25/35, SAM9M10/11, SAM9N11/12) processors. Its voltage rails, sequencing logic, and register mapping align precisely with the power architecture and boot requirements of these SoCs - confirmed in Qorvo's official datasheet Rev. G.
Does the ACT88760-101SR include an integrated battery charger?
Yes, the ACT88760-101SR integrates a full ActivePath™ battery charging system with ACIN detection, programmable charge current (via ISET resistor), thermal regulation, charge safety timers, and battery temperature monitoring (via TH pin). It supports Li-ion batteries and provides nSTAT output for direct LED status indication - no external charger IC is required.
What is the function of the VSEL pin on the ACT88760-101SR?
The VSEL pin on the ACT88760-101SR selects between primary and secondary output voltages for the three DC/DC regulators: logic low configures default VOUTx (e.g., 1.35V/1.2V/3.3V), while logic high enables standby VSTBYx (e.g., 1.5V/1.0V/3.3V). This hardware-selectable dual-voltage mode supports dynamic power states like suspend-to-RAM without I²C intervention.
How does the ACT88760-101SR handle power sequencing for SAMA5D3 processors?
The ACT88760-101SR implements hardware-controlled sequencing via nPBIN (master reset), PWRHLD (global regulator enable), and PWREN (individual rail control), complemented by register-programmable turn-on delays (0–255ms) for each DC/DC and LDO. This matches the strict voltage ramp order and timing windows specified in SAMA5D3 reference designs - eliminating need for external CPLDs or timing ICs.
Is the ACT88760-101SR pin-compatible with other Qorvo PMUs like the ACT8945A?
Yes, the ACT88760-101SR shares identical TQFN55-40 package, pin count (40), and pinout with the ACT8945A family - including matching VP1/VP2/VP3, SW1/SW2/SW3, OUT1–OUT7, and control signal assignments (nPBIN, PWRHLD, SCL/SDA, etc.). This allows drop-in replacement in existing layouts designed for ACT8945A variants.
ACT88760-101SR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Qorvo
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- -
- Current - Supply:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
ACT88760-101SR FAQ
1.How can I place an order for ACT88760-101SR through Aetrix?
Please submit a Request for Quotation (RFQ) for ACT88760-101SR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ACT88760-101SR reliable?
The price and inventory of ACT88760-101SR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ACT88760-101SR is usually 5 days.
3.What payment methods are accepted for ACT88760-101SR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ACT88760-101SR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ACT88760-101SR?
ACT88760-101SR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ACT88760-101SR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ACT88760-101SR?
For technical support, including ACT88760-101SR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ACT88760-101SR requirements.
6.How does Aetrix verify that ACT88760-101SR is sourced from the original manufacturer or authorized distributors?
All ACT88760-101SR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ACT88760-101SR meets industry standards.
7.What is the process for return or replacement of ACT88760-101SR?
All ACT88760-101SR units undergo pre-shipment inspection (PSI). If there is an issue with ACT88760-101SR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ACT88760-101SR part is unused and in its original packaging.
Return procedure for ACT88760-101SR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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