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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. AD13280AZ

Name: AD13280AZ
Brand: Analog Devices Inc.
SKU: AD13280AZ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD13280AZ

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 68-CLCC

Datasheet:: AD13280AZ.pdf

Description:: IC ADC 12BIT 68CLCC

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD13280AZ from Analog Devices is a dual-channel, 12-bit, 80 MSPS analog-to-digital converter with integrated analog input signal conditioning, on-chip track-and-hold, and laser-trimmed thin-film resistor networks for ±1% channel gain matching and 90 dB channel-to-channel isolation - deployed in radar I/Q baseband processing and GPS antijamming receivers.

For engineers reviewing the AD13280AZ datasheet, AD13280AZ pinout, AD13280AZ application, or AD13280AZ equivalent, this page delivers verified technical context, real-world timing and dynamic range specifications (e.g., 80 dB SFDR at 10 MHz, 66.5 dB SNR), package-validated pin functions, and two confirmed alternative ADCs for multichannel receiver designs requiring matched dual-channel sampling with DC-coupled signal conditioning.

Technical Context

The AD13280AZ implements a three-pipeline multipass architecture with on-board AD8045 amplifiers, AD8138 differential drivers, and a custom ADC core, enabling 12-bit resolution at 80 MSPS while maintaining <0.3 ps rms aperture jitter and 25 ns transient response. Each channel operates independently with separate ±5 V analog supplies (AVCC/AVEE) and 3.3 V digital output supply (DVCC).

Analog input flexibility includes selectable single-ended (±0.5 V or ±1.0 V via AMP-IN-A-1/AMP-IN-A-2) or differential (A+IN/A−IN, B+IN/B−IN) configurations, with integrated Nyquist filtering and 618 Ω differential input impedance. Output coding is twos complement with 3.3 V CMOS-compatible logic levels and 100 Ω series terminators.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12 bits - defines full-scale quantization step of 244 µV for ±1 V input range, enabling precise baseband digitization in radar and comms receivers.
Sample Rate	80 MSPS maximum - supports Nyquist sampling of signals up to 40 MHz; minimum rate of 30 MSPS allows flexible clocking in adaptive systems.
SFDR @ 10 MHz	75–80 dBFS - ensures spurious-free operation for high-fidelity I/Q demodulation without masking adjacent channels.
SNR @ 10 MHz	66.5–70 dBFS - delivers >10.7 effective number of bits (ENOB) for accurate amplitude measurement in GPS and phased array applications.
Channel Isolation	90 dB - prevents crosstalk-induced phase error between I and Q paths, critical for vector signal integrity in coherent receivers.
Aperture Jitter	0.3 ps rms - limits sampling uncertainty-induced noise floor degradation, preserving SNR at high input frequencies.
Power per Channel	1.85 W - total dissipation of 3.7 W at full operation; requires thermal management in dense RF front-end layouts.

Pinout & Package

AD13280AZ is housed in a 68-lead ceramic gull wing package (ES package), with θ_JA = 24.3°C/W and θ_JC = 2.2°C/W. Ground separation is enforced via dedicated AGNDA/AGNDB and DGNDA/DGNDB pins, and internal shield pins (1, 35) isolate A/B channels.

Pin/Terminal	Circuit Role	Design Meaning
A+IN / A−IN B+IN / B−IN	Differential analog inputs	Accept ±1 V p-p differential signals directly into AD8138 driver; 618 Ω nominal impedance enables 50 Ω system interface with minimal external matching.
AMP-IN-A-1 / AMP-IN-A-2 AMP-IN-B-1 / AMP-IN-B-2	Single-ended analog inputs	Selectable ±0.5 V (100 Ω) or ±1.0 V (200 Ω) full-scale ranges via laser-trimmed resistor dividers - eliminates need for external gain stages.
ENCODEA / ENCODEA ENCODEB / ENCODEB	Differential encode clock inputs	Accept 0.4 V p-p differential signals; rising edge initiates conversion; 4.75–8 ns pulse width requirement ensures setup/hold compliance at 80 MSPS.
D0A–D11A / D0B–D11B	Parallel digital outputs	12-bit twos complement words, 3.3 V CMOS-compatible, with internal 100 Ω series termination - simplifies PCB routing and reduces external component count.
DROUTA / DROUTB	Data ready strobes	Indicate valid data availability after 5 ns output delay; synchronize downstream FPGA or DSP capture logic to sampled data.

Key Features

Feature	Design Value
On-chip signal conditioning	Integrated AD8045 amplifier + AD8138 differential driver per channel eliminates discrete op-amp and filter components, reducing board area by >40% in I/Q receivers.
Channel-to-channel matching	±1% gain error and ±0.1% gain match across temperature - enables calibrated I/Q imbalance correction without per-channel calibration firmware.
DC-coupled analog path	Supports baseband digitization from 0 Hz - essential for GPS carrier-phase tracking and direct-conversion radar architectures.
Integral Nyquist filter	Single-pole low-pass response with ≤0.12 dB pass-band ripple to 25 MHz - suppresses aliasing without external anti-aliasing filters in 80 MSPS systems.
Independent channel power domains	Separate AVCC/AVEE and DVCC supplies per channel allow selective shutdown and independent voltage scaling - improves power management in multimode receivers.

Applications

Radar I/Q Baseband Processing	Phased Array Receivers
Use Scenario: Digitizing in-phase and quadrature (I/Q) outputs from zero-IF mixers in airborne radar front-ends operating at L- and S-bands. IC Role / Device Role / Timing Role: Dual-channel simultaneous sampling ADC with matched gain/phase response; provides time-aligned 12-bit samples for Doppler processing and beamforming. Use Value: 90 dB channel isolation and ±0.5% gain match preserve vector accuracy across I/Q paths, enabling sub-degree angle-of-arrival estimation.	Use Scenario: High-density antenna element digitization in ground-based phased arrays, where compact size and thermal stability are critical. IC Role / Device Role / Timing Role: Dual-channel ADC with integrated amplifiers and DC coupling - accepts direct outputs from low-noise amplifiers without AC coupling or gain staging. Use Value: On-chip 100 Ω/200 Ω input impedance options and ±0.5 V/±1.0 V ranges reduce external component count by 6–8 parts per channel versus discrete solutions.
GPS Antijamming Receivers	Communications Receivers
Use Scenario: Wideband digitization of GPS L1/L2 signals under jamming conditions, requiring high SFDR and low intermodulation distortion. IC Role / Device Role / Timing Role: Dual ADC capturing synchronized I/Q streams for adaptive nulling algorithms; 75 dB SFDR at 37 MHz suppresses strong out-of-band jammers. Use Value: 60 dBc two-tone IMD rejection at 36/37 MHz enables detection of weak GPS signals buried 60 dB below narrowband interference.	Use Scenario: Multistandard software-defined radio (SDR) front-end supporting LTE, WiMAX, and legacy cellular bands in base station transceivers. IC Role / Device Role / Timing Role: Dual ADC providing parallel digitization of diversity receive paths; 80 MSPS sample rate supports 40 MHz instantaneous bandwidth per channel. Use Value: 66.5 dB SNR at 21 MHz ensures >10-bit ENOB across 20 MHz LTE channel bandwidth, meeting EVM requirements for 256-QAM demodulation.

Radar I/Q Baseband Processing

Phased Array Receivers

Use Scenario: Digitizing in-phase and quadrature (I/Q) outputs from zero-IF mixers in airborne radar front-ends operating at L- and S-bands.

IC Role / Device Role / Timing Role: Dual-channel simultaneous sampling ADC with matched gain/phase response; provides time-aligned 12-bit samples for Doppler processing and beamforming.

Use Value: 90 dB channel isolation and ±0.5% gain match preserve vector accuracy across I/Q paths, enabling sub-degree angle-of-arrival estimation.

Use Scenario: High-density antenna element digitization in ground-based phased arrays, where compact size and thermal stability are critical.

IC Role / Device Role / Timing Role: Dual-channel ADC with integrated amplifiers and DC coupling - accepts direct outputs from low-noise amplifiers without AC coupling or gain staging.

Use Value: On-chip 100 Ω/200 Ω input impedance options and ±0.5 V/±1.0 V ranges reduce external component count by 6–8 parts per channel versus discrete solutions.

GPS Antijamming Receivers

Communications Receivers

Use Scenario: Wideband digitization of GPS L1/L2 signals under jamming conditions, requiring high SFDR and low intermodulation distortion.

IC Role / Device Role / Timing Role: Dual ADC capturing synchronized I/Q streams for adaptive nulling algorithms; 75 dB SFDR at 37 MHz suppresses strong out-of-band jammers.

Use Value: 60 dBc two-tone IMD rejection at 36/37 MHz enables detection of weak GPS signals buried 60 dB below narrowband interference.

Use Scenario: Multistandard software-defined radio (SDR) front-end supporting LTE, WiMAX, and legacy cellular bands in base station transceivers.

IC Role / Device Role / Timing Role: Dual ADC providing parallel digitization of diversity receive paths; 80 MSPS sample rate supports 40 MHz instantaneous bandwidth per channel.

Use Value: 66.5 dB SNR at 21 MHz ensures >10-bit ENOB across 20 MHz LTE channel bandwidth, meeting EVM requirements for 256-QAM demodulation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, high-SFDR ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9233-80	Single-channel, 12-bit, 80 MSPS; no integrated analog conditioning; requires external amplifier and reference.	Lacks on-chip gain/impedance matching and channel isolation - unsuitable for I/Q systems requiring matched pair performance.	Choose when space permits discrete signal chain design and channel matching is handled externally via calibration.
ADS5272	Dual-channel, 12-bit, 65 MSPS; integrated analog front-end but lower SFDR (72 dBFS @ 10 MHz) and no DC coupling.	AC-coupled only; cannot support GPS carrier-phase or zero-IF radar baseband applications requiring DC response.	Prefer for cost-sensitive, lower-bandwidth communications receivers where DC offset is not required.

Compared with AD13280AZ, AD9233-80 demands external signal conditioning and offers no channel matching, while ADS5272 trades 15 MSPS bandwidth and DC coupling for lower power - making AD13280AZ uniquely suited for high-isolation, DC-coupled, dual-channel radar and GNSS front-ends.

Availability

AD13280AZ is available at Aetrix Electronics and suitable for radar processing, GPS antijamming, and phased array receivers requiring stable component supply, long-term obsolescence mitigation, and traceable sourcing for defense and aerospace programs.

Supply support for AD13280AZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.

The AD13280AZ belongs to Analog Devices' high-speed precision ADC product line, engineered specifically for demanding RF receiver applications where dual-channel matching, DC coupling, and integrated signal conditioning are mandatory - not optional.

FAQ

What is the guaranteed maximum sample rate for the AD13280AZ?

The AD13280AZ guarantees a maximum conversion rate of 80 MSPS across its full operating temperature range (−40°C to +85°C), with parametric testing performed at this rate. Minimum conversion rate is 30 MSPS, allowing flexible clocking in adaptive systems. The AD13280AZ maintains specified SNR and SFDR performance only when operated within these bounds.

Does the AD13280AZ support DC-coupled analog inputs?

Yes, the AD13280AZ supports true DC-coupled operation in both single-ended (via AMP-IN-A-1/AMP-IN-A-2) and differential (via A+IN/A−IN) modes. Its analog input stage is designed for 0 Hz to 143 MHz bandwidth in single-ended mode and 0 Hz to 50 MHz in differential mode, enabling baseband digitization in GPS carrier-phase tracking and zero-IF radar systems.

What are the power supply requirements for the AD13280AZ?

The AD13280AZ requires three independent supplies: ±5.0 V (AVCC = +5 V, AVEE = −5 V) for analog signal conditioning and ADC core, and +3.3 V (DVCC) for digital outputs. Total power dissipation is 3.7–4.3 W, with 1.85 W per channel. Supply voltages must remain within AVCC: 4.85–5.25 V, AVEE: −5.25 to −4.75 V, and DVCC: 3.135–3.465 V to maintain rated ac performance.

How does the AD13280AZ achieve 90 dB channel-to-channel isolation?

The AD13280AZ achieves 90 dB channel isolation through physical separation: dedicated analog and digital ground pins (AGNDA/AGNDB, DGNDA/DGNDB), internal shield pins (1, 35), and independent power domains (AVCCA/AVCCB, AVEEA/AVEEB). This layout, combined with laser-trimmed thin-film resistor networks, minimizes capacitive and conductive coupling between A and B channels - verified by grounding one channel while applying full-scale signal to the other.

What is the function of the DROUTA and DROUTB pins on the AD13280AZ?

DROUTA and DROUTB are asynchronous data-ready strobes that go high 5 ns after the rising edge of ENCODEA or ENCODEB, indicating valid 12-bit output data (D0A–D11A or D0B–D11B) is present on the bus. These signals synchronize FPGA or DSP capture logic to sampled data, eliminating need for fixed-delay pipelines - a key timing advantage in real-time radar and communications receivers using the AD13280AZ.

AD13280AZ Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 68-CLCC

Packaging:: Tray

Product Status:: Obsolete

Number of Bits:: 12

Sampling Rate (Per Second):: 80M

Number of Inputs:: -

Input Type:: -

Data Interface:: Parallel

Configuration:: -

Ratio - S/H:ADC:: -

Number of A/D Converters:: 2

Architecture:: -

Reference Type:: -

Voltage - Supply, Analog:: -

Voltage - Supply, Digital:: -

Features:: -

Operating Temperature:: -25°C ~ 85°C

Supplier Device Package:: 68-CLCC (24.13x24.13)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

AD13280AZ FAQ

1.How can I place an order for AD13280AZ through Aetrix?

Please submit a Request for Quotation (RFQ) for AD13280AZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD13280AZ reliable?

The price and inventory of AD13280AZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD13280AZ is usually 5 days.

3.What payment methods are accepted for AD13280AZ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD13280AZ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD13280AZ?

AD13280AZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD13280AZ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD13280AZ?

For technical support, including AD13280AZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD13280AZ requirements.

6.How does Aetrix verify that AD13280AZ is sourced from the original manufacturer or authorized distributors?

All AD13280AZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD13280AZ meets industry standards.

7.What is the process for return or replacement of AD13280AZ?

All AD13280AZ units undergo pre-shipment inspection (PSI). If there is an issue with AD13280AZ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD13280AZ part is unused and in its original packaging.

Return procedure for AD13280AZ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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