Analog Devices Inc. AD1836AAS
- Part No.:
- AD1836AAS
- Manufacturer:
- Analog Devices Inc.
- Category:
- CODECS
- Package:
- 52-QFP
- Datasheet:
-
AD1836AAS.pdf
- Description:
- IC CODEC 4ADC/6DAC 24 BIT 52MQFP
- Quantity:
- Payment:

- Shipping:

Inventory:174
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD1836AAS from Analog Devices is a multichannel 96 kHz audio codec IC featuring three stereo DACs and two stereo ADCs, 24-bit resolution, A-weighted dynamic range of 100–105 dB (RMS), –92 dB THD+N for ADCs and –95 dB THD+N for DACs, and differential analog I/O for noise immunity - deployed in home theater systems for high-fidelity multichannel playback and recording.
For engineers reviewing the AD1836AAS datasheet, AD1836AAS pinout, AD1836AAS application, or AD1836AAS equivalent, key selection considerations include A-weighted SNR performance, 52-lead MQFP package compatibility, TDM 8-in/8-out auxiliary interface support, SPI-controlled volume ramping, and programmable PGA gain for ADC inputs.
Technical Context
The AD1836AAS implements patented multibit Σ-Δ architecture with independent decimation (ADC) and interpolation (DAC) filters - each offering 120 dB stop-band attenuation and linear phase response. Its dual ADC section supports three input configurations: direct differential, PGA-differential, and MUX/PGA single-ended, all configurable via SPI registers.
DAC operation supports I²S, left/right-justified, DSP, and packed TDM modes (128/256), enabling full 6-channel data routing over one DSDATA pin. Clock architecture accepts 256×/512×/768× fS master clock inputs and includes internal clock doubling for 96 kHz mode at 256× fS external frequency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC Resolution | 24-bit - enables high-resolution capture with >100 dB dynamic range under A-weighting. |
| DAC Dynamic Range (A-weighted) | 105–108 dB RMS - ensures low-noise playback suitable for premium audio equipment. |
| THD+N (ADC) | –92 dB typical - meets professional-grade distortion requirements for studio and broadcast applications. |
| THD+N (DAC) | –95 dB typical - exceeds CD-quality linearity for consumer and prosumer DAC stages. |
| Sample Rate Support | Up to 96 kHz - allows high-resolution audio processing without external oversampling. |
| Serial Interface Modes | I²S, left/right-justified, DSP, packed TDM - provides flexible integration with SHARC® SPORT and other DSPs. |
| Volume Control | 1023 linear steps, 0.098% step size, 60 dB max attenuation - enables precise digital gain matching across channels. |
| Power Supply | 5 V AVDD/DVDD, 3.3/5 V ODVDD - supports mixed-voltage system interfacing with logic-level flexibility. |
Pinout & Package
AD1836AAS is housed in a 52-lead MQFP (PQFP) plastic package with 0.65 mm lead pitch, thermally enhanced for audio-grade thermal management (θJA = 45°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DVDD (Pins 1, 40) | Digital power supply | 5 V rail for digital core and control logic; requires local 100 nF + 22 µF bypassing. |
| AVDD (Pins 10, 15) | Analog power supply | 5 V rail for ADC/DAC analog sections; must be isolated from DVDD for optimal SNR. |
| FILTR (Pin 13) | Voltage reference filter | Bypass with 10 µF||100 nF to AGND; supplies ~2.25 V bias for external op-amp common-mode level setting. |
| ADC1INLP/LN/RP/RN (Pins 16–19) | Primary ADC differential inputs | High-performance 4-channel input pair; requires 100 Ω series + 1 nF NPO grounding per pin. |
| DSDATA1/2/3 (Pins 38–42) | DAC serial data inputs | Three independent 24-bit stereo data lanes; support TDM-packed mode for 6-channel consolidation. |
| OUTLP1–3 / OUTLN1–3 (Pins 4–9, 30–35) | DAC differential outputs | Six fully differential outputs (±1.4 V swing at 0 dBFS); require external third-order LPF for anti-aliasing and SE conversion. |
| CCLK / CLATCH / CDATA / COUT (Pins 2–3, 49–51) | SPI control interface | 4-wire Motorola-compatible port (16-bit words); max 8 MHz clock; write-only registers except ADC peak read-back. |
Key Features
| Feature | Design Value |
|---|---|
| A-weighted dynamic range (ADC) | 100–105 dB RMS - directly improves audible signal fidelity in noise-sensitive listening environments. |
| Programmable PGA gain (ADC2) | 0–12 dB in 3 dB steps - enables matched gain staging between microphone and line-level sources without external amplifiers. |
| Digital de-emphasis | Configurable per DAC channel - corrects pre-emphasized CD/DVD source material without added analog circuitry. |
| Auto-ramp volume control | Glitch-free attenuation transitions - eliminates audible clicks during real-time gain changes in mixer or EQ applications. |
| TDM auxiliary interface | Supports 8-in/8-out glueless SHARC® SPORT connection - reduces PCB routing complexity and eliminates external multiplexers in DSP-based systems. |
| Soft power-down mode | Reduces analog current to 47 mA while retaining register state - enables fast wake-up in portable or low-power audio subsystems. |
Applications
| Home Theater Audio Processing | Automotive Infotainment System |
|---|---|
Use Scenario: Multichannel decoding and upmixing of Dolby Digital and DTS bitstreams in AV receivers. IC Role / Device Role / Timing Role: Primary audio codec handling simultaneous 6-channel DAC playback and 4-channel ADC recording with synchronized TDM framing. Use Value: Differential outputs reduce EMI susceptibility in densely routed chassis; A-weighted 105 dB DR preserves dialog clarity in noisy living environments. |
Use Scenario: Front/rear seat audio zone separation with independent volume and EQ control in premium vehicle head units. IC Role / Device Role / Timing Role: Dual ADC pairs acquire microphone and line inputs; three DAC pairs drive front, rear, and subwoofer amplifiers with independent digital attenuation. Use Value: SPI-controlled auto-ramp prevents click artifacts during driver-adjusted volume sweeps; 96 kHz capability supports high-res streaming audio decoding. |
| DVD Recorder Audio I/O | Digital Audio Effects Processor |
Use Scenario: Simultaneous analog-to-digital conversion of stereo line input and digital-to-analog conversion of encoded AC-3 output during DVD authoring. IC Role / Device Role / Timing Role: ADC1 captures analog source; DAC1/DAC2 reconstruct L/R and surround channels; DAC3 handles center/sub outputs. Use Value: 24-bit resolution and –95 dB THD+N ensure archival-quality audio fidelity; programmable de-emphasis restores original CD mastering characteristics. |
Use Scenario: Real-time multi-effects processing (reverb, chorus, delay) on live instrument signals using SHARC DSP with minimal latency. IC Role / Device Role / Timing Role: Acts as high-bandwidth audio I/O bridge between SHARC SPORT and analog stage; TDM auxiliary mode enables full 8-in/8-out throughput. Use Value: 120 dB ADC filter stop-band attenuation prevents aliasing artifacts in time-domain effects; differential I/O maintains SNR despite high-gain DSP feedback paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multichannel audio codec applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK4118VN | 24-bit, 192 kHz capable, but only 2× stereo ADC/DAC; no PGA; uses QFN-48 package. | Lacks secondary ADC input flexibility and TDM auxiliary mode; suited for simpler stereo+surround systems. | Select when higher sample rate (192 kHz) is prioritized over multichannel I/O count and programmable gain. |
| CS42526-CQZ | 24-bit, 192 kHz, 6-in/8-out, integrated jack detection; uses 64-pin LQFP; no A-weighted DR spec published. | Includes analog switch matrix and GPIOs for headset/speaker detection; optimized for portable media players. | Select when system-level integration (jack sense, pop/click suppression) outweighs A-weighted SNR optimization for fixed-installation audio. |
Compared with AK4118VN and CS42526-CQZ, AD1836AAS uniquely delivers A-weighted 105 dB ADC dynamic range, dual-mode ADC2 (PGA/MUX), and SHARC SPORT-compatible TDM auxiliary interface - making it optimal for high-SNR, programmable, DSP-coupled multichannel audio systems where precision analog front-end control is critical.
Availability
AD1836AAS is available at Aetrix Electronics and suitable for home theater systems, automotive infotainment platforms, and DVD recorder designs requiring stable component supply, long-lifecycle assurance, and consistent parametric performance across production batches.
Supply support for AD1836AAS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide.
The AD1836AAS belongs to Analog Devices' high-fidelity audio codec product line, engineered specifically for multichannel consumer and professional audio systems demanding low THD+N, high dynamic range, and flexible digital interface options.
FAQ
What distinguishes AD1836AAS from the standard AD1836A?
The AD1836AAS is the specific variant of the AD1836A codec characterized with A-weighted dynamic range performance: 100–105 dB (ADC) and 105–108 dB (DAC), measured per Table 2 of the Rev. A datasheet. This specification differentiates it from the AD1836ACS variant, which has lower A-weighted DR (97–102 dB). All functional, pinout, and register behavior remains identical between AD1836AAS and AD1836ACS - only the guaranteed analog performance bin differs.
Does AD1836AAS support 96 kHz operation across all ADC and DAC channels?
AD1836AAS supports 96 kHz sample rate, but with channel limitations: only the primary stereo ADC pair (ADC1L/R) and all three stereo DAC pairs operate at 96 kHz simultaneously. The secondary ADC pair (ADC2) is restricted to 48 kHz in 96 kHz system mode. This is explicitly defined in the Functional Overview section (Page 11) and confirmed by the ADC decimation ratio (64× for 96 kHz vs. 128× for 48 kHz) in the datasheet.
Can AD1836AAS interface directly with a SHARC processor's SPORT without external logic?
Yes - AD1836AAS supports a dedicated TDM auxiliary interface mode that enables glueless connection to a single SHARC SPORT, providing full 8-in/8-out capability. In this mode, pins like ABCLK, ALRCLK, DSDATA1–3, and ASDATA1–2 are reconfigured per Table 11, allowing the AD1836AAS to act as an 8-channel audio I/O expansion for the SHARC without multiplexers or level shifters.
What is the purpose of the FILTD and FILTR pins on AD1836AAS?
FILTR (Pin 13) is the voltage reference output (~2.25 V), used to bias external op-amps driving ADC inputs or receiving DAC outputs - it must be bypassed with 10 µF||100 nF to AGND. FILTD (Pin 12) is a dedicated DAC bias noise filter node, connected to a grounded capacitor to suppress internal DAC reference noise; its omission may slightly increase DAC output noise floor but is permissible in less demanding applications.
Is the SPI interface of AD1836AAS compatible with standard microcontroller peripherals?
Yes - AD1836AAS implements a 4-wire SPI-compatible control port (CCLK, CLATCH, CDATA, COUT) with Motorola-style timing and 16-bit word length. It operates asynchronously to audio clocks, supports up to 8 MHz CCLK, and is compatible with most MCU SPI peripherals when configured for CPOL=0, CPHA=0, MSB-first. However, due to an interface anomaly, writes to DAC registers immediately after ADC register reads/writes must be repeated twice to ensure execution.
AD1836AAS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-QFP
- Packaging:
- Bag
- Product Status:
- Obsolete
- Type:
- General Purpose
- Data Interface:
- Serial
- Resolution (Bits):
- 24 b
- Number of ADCs / DACs:
- 4 / 6
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 105 / 108
- Dynamic Range, ADCs / DACs (db) Typ:
- 105 / 108
- Voltage - Supply, Analog:
- 4.75V ~ 5.25V
- Voltage - Supply, Digital:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-MQFP (10x10)
AD1836AAS FAQ
1.How can I place an order for AD1836AAS through Aetrix?
Please submit a Request for Quotation (RFQ) for AD1836AAS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD1836AAS reliable?
The price and inventory of AD1836AAS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD1836AAS is usually 5 days.
3.What payment methods are accepted for AD1836AAS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD1836AAS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD1836AAS?
AD1836AAS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD1836AAS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD1836AAS?
For technical support, including AD1836AAS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD1836AAS requirements.
6.How does Aetrix verify that AD1836AAS is sourced from the original manufacturer or authorized distributors?
All AD1836AAS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD1836AAS meets industry standards.
7.What is the process for return or replacement of AD1836AAS?
All AD1836AAS units undergo pre-shipment inspection (PSI). If there is an issue with AD1836AAS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD1836AAS part is unused and in its original packaging.
Return procedure for AD1836AAS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD1836AAS Tags

-
NAU88C22YG
Nuvoton Technology Corporation

-
TLV320AIC3100IRHBR
Texas Instruments

-
DA7212-01UM2
Renesas

-
NAU8810YG
Nuvoton Technology Corporation

-
DA7218-00U32
Renesas

-
CMX655DQ6-TR1K
CML Micro

-
SGTL5000XNLA3
NXP Semiconductors

-
TLV320AIC3104IRHBR
Texas Instruments

-
MAX9867EWV+T
Analog Devices Inc./Maxim Integrated

-
MAX9860ETG+T
Analog Devices Inc./Maxim Integrated

-
TLV320AIC3106IRGZR
Texas Instruments

-
SGTL5000XNLA3R2
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

