Analog Devices Inc. AD1836AASRL
- Part No.:
- AD1836AASRL
- Manufacturer:
- Analog Devices Inc.
- Category:
- CODECS
- Package:
- 52-QFP
- Datasheet:
-
AD1836AASRL.pdf
- Description:
- IC CODEC 4ADC/6DAC 24 BIT 52MQFP
- Quantity:
- Payment:

- Shipping:

Inventory:703
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Product details
Overview
AD1836AASRL from Analog Devices is a multichannel 96 kHz audio codec IC integrating three stereo DACs (6 channels) and two stereo ADCs (4 channels) in a single 52-lead MQFP package. It supports 24-bit resolution, 96 kHz sample rate, differential analog I/O, on-chip volume control with auto-ramp, and programmable gain amplifiers for ADC inputs. It is deployed in home theater systems requiring high-fidelity multichannel audio conversion.
For engineers reviewing the AD1836AASRL datasheet, AD1836AASRL pinout, AD1836AASRL application, or AD1836AASRL equivalent, this page delivers verified specifications, functional context, real-world use cases, and validated alternative options for professional audio system design and BOM optimization.
Technical Context
The AD1836AASRL implements patented multibit Σ-Δ architecture across all six DAC and four ADC channels, with independent digital filters: decimation filters (120 dB stop-band attenuation, linear phase) for ADCs and interpolation filters (70 dB stop-band attenuation) for DACs. Clocking supports flexible master clock ratios (256×/512×/768× fS) and dual-domain operation-5 V analog/digital supplies with separate ODVDD for logic-level output drivers.
Its serial interface includes an SPI port for register configuration (volume, gain, mute, de-emphasis), three independent DAC data ports (DSDATA1–3) or TDM-packed mode for 8-channel I/O, and auxiliary mode enabling glueless SHARC® SPORT interfacing for 8-in/8-out expansion. ADCs support three input configurations: direct differential, PGA differential, and MUX/PGA single-ended.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC Channels | 4 total (2 stereo pairs): primary pair fully differential; secondary pair configurable via SPI for direct, PGA, or MUX/PGA input modes |
| DAC Channels | 6 total (3 stereo pairs), each with independent 1024-step linear volume control and differential outputs |
| Resolution & Sample Rate | 24-bit data width; supports 48 kHz (all 8 channels) or 96 kHz (primary 4 channels active) |
| Analog Performance | ADC: 105 dB SNR (A-weighted), –92 dB THD+N; DAC: 108 dB SNR (A-weighted), –95 dB THD+N |
| Power Supplies | AVDD/DVDD = 4.75–5.25 V; ODVDD = 3.0–5.25 V; analog current = 108 mA, digital current = 78 mA |
| Digital Interface | SPI control port (≤8 MHz); I²S/right/left-justified/DSP/TDM serial data formats; auxiliary mode for SHARC SPORT integration |
| Package | 52-lead MQFP (PQFP), 10 mm × 10 mm body, 0.65 mm pitch |
Pinout & Package
AD1836AASRL is housed in a 52-lead MQFP (plastic quad flat pack) with 0.65 mm lead pitch and 10 mm × 10 mm body size. Pin 1 is marked by a corner notch; thermal resistance θJA = 45°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 40, 39, 52 | DVDD / DGND | Digital power supply (5 V) and ground return-bypass with 100 nF ceramic near each pin to suppress digital switching noise |
| 10, 15, 11, 14, 28, 29 | AVDD / AGND | Analog power and ground-separate from digital domain to prevent coupling; requires bulk + ceramic bypassing |
| 4–9, 30–35 | OUTLPx / OUTLNx / OUTRPx / OUTRNx | Differential analog outputs for DACs 1–3; each pair swings ±1.4 V around FILTR (~2.25 V) reference |
| 16–19, 20–27 | ADC1INLP/RN/RP/RN, ADC2INxx | Differential and configurable single-ended ADC inputs; secondary inputs support PGA gain (0–12 dB in 3 dB steps) |
| 36–37, 43–44, 38–42, 47–48 | DLRCLK/DBCLK, ALRCLK/ABCLK, DSDATA1–3, ASDATA1–2 | Independent LR/bit clocks and data lanes for DAC/ADC domains; supports TDM packing for consolidated 8-channel I/O |
| 2, 3, 49–51 | CDATA, PD/RST, COUT, CLATCH, CCLK | 4-wire SPI interface: bidirectional control data, active-low reset, and synchronous latch/clock for register writes |
| 12–13, 46 | FILTD, FILTR, ODVDD | FILTD filters DAC bias noise; FILTR provides 2.25 V reference for external op-amp biasing; ODVDD powers digital output drivers (3.3 V or 5 V selectable) |
Key Features
| Feature | Design Value |
|---|---|
| Triple stereo DAC + dual stereo ADC | Enables full 5.1/6.1/7.1 channel audio playback and recording in one IC-reduces board space and inter-chip timing skew |
| 24-bit/96 kHz capability | Supports studio-grade audio fidelity and DVD-Audio compliance without external oversampling or sample-rate conversion |
| Differential analog I/O | Improves PSRR and common-mode noise rejection (>110 dB interchannel isolation) for cleaner signal integrity in noisy PCB environments |
| On-chip PGA and auto-ramp volume | Eliminates need for external gain stages and analog mute circuits-reduces component count and click/pop artifacts during level transitions |
| Auxiliary interface mode | Allows direct connection to SHARC SPORT for 8-in/8-out expansion without glue logic-enables scalable audio processing architectures |
Applications
| Home Theater Audio | Automotive Infotainment |
|---|---|
Use Scenario: 7.1-channel surround sound decoding and playback in AV receivers and media processors. IC Role / Device Role / Timing Role: Primary multichannel audio codec handling simultaneous DAC playback (3 stereo pairs) and ADC capture (2 stereo pairs) with synchronized TDM framing. Use Value: Single-chip integration reduces latency between channels and eliminates inter-device clock domain mismatches critical for lip-sync accuracy. | Use Scenario: High-fidelity cabin audio system with microphone array input and multi-zone speaker output. IC Role / Device Role / Timing Role: ADC front-end for noise-cancelling microphones (using PGA mode) and DAC driver for amplified speaker zones with independent volume control per channel. Use Value: Programmable 0–12 dB PGA gain enables consistent SNR across varying mic sensitivities; differential outputs reject engine EMI. |
| DVD Recorder Audio Path | Digital Audio Effects Processor |
Use Scenario: Simultaneous analog-to-digital conversion of stereo line-in and digital-to-analog conversion of encoded Dolby Digital streams. IC Role / Device Role / Timing Role: Dual-role codec performing real-time ADC acquisition at 48 kHz and DAC playback at 96 kHz using independent clock domains. Use Value: Independent sample rate support allows legacy analog source digitization while maintaining high-res playback-no external SRC required. | Use Scenario: Low-latency audio effects chain (reverb, EQ, compression) implemented on SHARC DSP with full 8-channel I/O. IC Role / Device Role / Timing Role: Auxiliary mode interface bridging SHARC SPORT to 4 ADC + 4 DAC channels using single TDM frame sync and bit clock. Use Value: Glueless SHARC integration avoids FPGA or level-shifter components-reduces BOM cost and layout complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multichannel audio codec applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK4118VN | 4 ADC / 8 DAC channels; supports 192 kHz; no integrated PGA; uses 3.3 V core supply | Better suited for ultra-high-res playback-only systems; lacks ADC input flexibility for microphone pre-amplification | Select AK4118VN when maximum DAC channel count and 192 kHz playback are prioritized over ADC configurability and 5 V compatibility. |
| CS42526-CQZ | 6 ADC / 8 DAC channels; 192 kHz; integrated headphone amp; SPI/I²C control; 3.3 V only | Targeted at portable and mixed-signal designs requiring headphone drive; not pin-compatible and lacks differential ADC inputs | Choose CS42526-CQZ for battery-powered or compact embedded audio with headphone output-avoid if differential ADC performance or 5 V operation is mandatory. |
Compared with AK4118VN and CS42526-CQZ, AD1836AASRL uniquely balances 5 V operation, configurable ADC input topologies (including PGA), and true differential I/O across all channels-making it optimal for industrial and automotive audio systems where supply robustness and noise immunity are critical.
Availability
AD1836AASRL is available at Aetrix Electronics and suitable for home theater systems, automotive infotainment units, and professional audio equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for AD1836AASRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and connectivity.
The AD1836AASRL belongs to Analog Devices' high-fidelity audio codec product line, engineered for multichannel consumer and automotive audio systems demanding low THD+N, high SNR, and flexible digital audio interfacing.
FAQ
What is the maximum sample rate supported by the AD1836AASRL for full 8-channel operation?
The AD1836AASRL supports 48 kHz sample rate with all eight channels (four ADC + six DAC, though only four DAC channels active in full TDM mode) simultaneously operational. At 96 kHz, only the primary two stereo ADCs and three stereo DACs remain active-totaling six channels-to maintain oversampling ratio and dynamic range. This is confirmed in the Functional Overview section of the Rev. A datasheet.
Does the AD1836AASRL support I²S format on both ADC and DAC serial ports by default?
Yes, the AD1836AASRL defaults to I²S format on both ADC and DAC serial ports at power-up. ADC Control Register 2 Bits 8–9 and DAC Control Register 1 Bits 5–7 allow reconfiguration to right-justified, left-justified, DSP, or packed modes. The I²S delay of one BCLK cycle from LRCLK edge is maintained unless modified via register programming.
Can the AD1836AASRL's ADC inputs accept single-ended signals without external circuitry?
No-the AD1836AASRL ADC inputs require differential signaling for optimal performance. The secondary ADC pair supports single-ended operation only in MUX/PGA mode, but even then, external RC filtering (100 Ω + 1 nF to AGND) is mandatory per datasheet Figure 11 and Functional Overview to suppress switched-capacitor glitches. Direct single-ended drive violates input voltage and CMRR specifications.
What is the function of the FILTR pin on the AD1836AASRL, and how must it be decoupled?
The FILTR pin on the AD1836AASRL provides the internal 2.25 V voltage reference used to bias differential ADC/DAC input and output stages. It must be decoupled with a parallel 10 µF tantalum (or aluminum electrolytic) and 100 nF ceramic capacitor directly to AGND, placed as close as possible to Pin 13. Drawing >50 µA from FILTR risks reference drift and degraded THD+N performance.
Is the AD1836AASRL pin-compatible with the AD1836ACS or other variants in the AD1836 family?
Yes, the AD1836AASRL is pin-compatible with AD1836ACS and AD1836AST, all sharing the identical 52-lead MQFP package and pinout per Table 10 of the Rev. A datasheet. Differences are limited to temperature grade (ASRL = industrial, –40°C to +85°C ambient) and minor analog performance specs (e.g., SNR tolerance), not physical or electrical pin mapping.
AD1836AASRL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-QFP
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- General Purpose
- Data Interface:
- Serial
- Resolution (Bits):
- 24 b
- Number of ADCs / DACs:
- 4 / 6
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 105 / 108
- Dynamic Range, ADCs / DACs (db) Typ:
- 105 / 108
- Voltage - Supply, Analog:
- 4.75V ~ 5.25V
- Voltage - Supply, Digital:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-MQFP (10x10)
AD1836AASRL FAQ
1.How can I place an order for AD1836AASRL through Aetrix?
Please submit a Request for Quotation (RFQ) for AD1836AASRL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD1836AASRL reliable?
The price and inventory of AD1836AASRL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD1836AASRL is usually 5 days.
3.What payment methods are accepted for AD1836AASRL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD1836AASRL transactions.
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4.How is shipping managed for AD1836AASRL?
AD1836AASRL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD1836AASRL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD1836AASRL?
For technical support, including AD1836AASRL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD1836AASRL requirements.
6.How does Aetrix verify that AD1836AASRL is sourced from the original manufacturer or authorized distributors?
All AD1836AASRL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD1836AASRL meets industry standards.
7.What is the process for return or replacement of AD1836AASRL?
All AD1836AASRL units undergo pre-shipment inspection (PSI). If there is an issue with AD1836AASRL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD1836AASRL part is unused and in its original packaging.
Return procedure for AD1836AASRL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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