Analog Devices Inc. AD1836ACS
- Part No.:
- AD1836ACS
- Manufacturer:
- Analog Devices Inc.
- Category:
- CODECS
- Package:
- 52-QFP
- Datasheet:
-
AD1836ACS.pdf
- Description:
- MULTICHANNEL 96 KHZ CODEC
- Quantity:
- Payment:

- Shipping:

Inventory:8,334
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Product details
Overview
AD1836ACS from Analog Devices is a 5 V, multichannel audio codec IC with three stereo DACs and two stereo ADCs, supporting 24-bit/96 kHz operation and featuring A-weighted dynamic range of 97–102 dB (RMS), differential outputs for noise immunity, and SPI-based volume control with auto-ramp. It targets high-fidelity consumer audio systems requiring precise multichannel analog I/O.
For engineers reviewing the AD1836ACS datasheet, AD1836ACS pinout, AD1836ACS application, or AD1836ACS equivalent, key selection considerations include its 52-lead MQFP package, dual ADC input mode flexibility (direct/PGA/MUX), TDM-capable serial ports for 8-in/8-out expansion, and A-weighted filter configuration confirmed for this variant.
Technical Context
The AD1836ACS implements patented multibit Σ-∆ architecture across six DAC channels and four ADC channels, with independent decimation (120 dB stop-band attenuation) and interpolation filters. Its ADC section supports 96 kHz sampling on primary channels only, while secondary ADCs operate at 48 kHz in programmable modes (direct differential, PGA, or MUX).
It features three independent serial data inputs (DSDATA1–3) for DACs and two serial outputs (ASDATA1–2) for ADCs, plus auxiliary interface pins enabling glueless SHARC® SPORT integration for 8-channel TDM. Clocking supports 256×/512×/768× fS master clock ratios, with internal clock generation via doubler in non-256× modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC Resolution | 24-bit-enables high-resolution capture with >100 dB SNR in A-weighted mode. |
| DAC THD + N | –95 dB (0 dBFS)-ensures low distortion in high-fidelity playback paths. |
| ADC Dynamic Range (A-weighted) | 97–102 dB RMS-meets professional-grade audio SNR requirements for consumer AV equipment. |
| Sample Rate Support | Up to 96 kHz-supports DVD-Audio, SACD, and high-res streaming formats. |
| Serial Interface Modes | I²S, left/right justified, DSP, and packed TDM (128/256)-enables flexible SoC/DSP interfacing without glue logic. |
| Volume Control | 1023 linear steps (0.098% step size, 60 dB range)-provides smooth, clickless attenuation for user-facing controls. |
| Power Supply | 5 V AVDD/DVDD, 3.3/5 V ODVDD-allows mixed-voltage system integration with TTL/CMOS-compatible I/O. |
Pinout & Package
AD1836ACS is housed in a 52-lead MQFP (PQFP) plastic package with exposed thermal pad, optimized for audio PCB layout and thermal management in space-constrained AV receivers and set-top boxes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ADC1INLP / ADC1INLN | Primary ADC left differential input | Direct-switched-capacitor interface requiring external 100 Ω + 1 nF filtering for optimal THD+N performance. |
| DSDATA1 / DSDATA2 / DSDATA3 | DAC serial data inputs (stereo pair each) | Enable independent stereo stream routing to DAC1–DAC3 without time-division multiplexing overhead. |
| OUTLP1 / OUTLN1 – OUTRP3 / OUTRN3 | Six fully differential DAC outputs | Provide ±1.4 V swing around FILTR (~2.25 V common-mode) for low-noise, high-PSRR analog output stages. |
| FILTR / FILTD | Voltage reference and DAC bias filter pins | Require 10 µF || 100 nF bypassing to stabilize internal bias and reduce DAC output noise floor. |
| PD/RST | Active-low power-down/reset | Resets all registers and initiates ~4500-MCLK initialization sequence; retains analog bias during soft power-down. |
Key Features
| Feature | Design Value |
|---|---|
| A-weighted dynamic range (ADC) | 97–102 dB RMS-meets IEC 60651 Class 1 accuracy for precision audio measurement and broadcast monitoring. |
| Programmable PGA gain (ADC2) | 0–12 dB in 3 dB steps-enables direct connection of low-level microphone or line inputs without external amplification. |
| TDM auxiliary interface | Supports 8-in/8-out via single SHARC SPORT-eliminates external multiplexers in multi-DSP audio processing architectures. |
| Digital de-emphasis | Configurable per DAC channel-restores frequency response for legacy CD digital sources without external filters. |
| Clickless mute & auto-ramp volume | Hardware-assisted transitions-prevents audible pop/click during real-time volume changes in UI-controlled systems. |
Applications
| Home Theater Receivers | Automotive Infotainment |
|---|---|
Use Scenario: Multichannel decoding and post-processing of Dolby Digital and DTS bitstreams in AV receivers. IC Role / Device Role / Timing Role: Primary audio codec handling 6-channel DAC output (front L/R, center, surround L/R, subwoofer) and 2-channel ADC feedback for room correction. Use Value: A-weighted 102 dB dynamic range ensures quiet background passages remain resolved amid high-SPL effects, critical for THX-certified playback. |
Use Scenario: Audio hub in head-unit systems integrating Bluetooth streaming, USB playback, and analog radio tuner inputs. IC Role / Device Role / Timing Role: Central analog I/O interface managing 4-channel ADC (mic/tuner) and 6-channel DAC (speaker outputs + subwoofer). Use Value: PGA programmability allows unified gain staging across diverse input sources (e.g., 10 mV mic vs. 1 V line), reducing BOM count. |
| DVD/Blu-ray Recorders | Digital Audio Effects Processors |
Use Scenario: High-fidelity analog capture and re-encoding of legacy analog video/audio sources into digital formats. IC Role / Device Role / Timing Role: Dual ADC path (primary + secondary) simultaneously digitizing composite video sync and stereo audio with sample-accurate timing alignment. Use Value: 96 kHz support enables archival-quality PCM capture exceeding CD standard, preserving transient detail in remastered content. |
Use Scenario: Real-time multi-effects engine applying reverb, chorus, and EQ to live instrument signals in stage gear. IC Role / Device Role / Timing Role: Low-latency ADC/DAC bridge between analog front-end and FPGA/DSP processing pipeline using TDM-packed data mode. Use Value: Packed Mode 256 reduces serial port count to one DAC input and one ADC output, simplifying high-channel-count PCB routing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multichannel audio codec applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK4118VN | 24-bit/192 kHz, 2 ADC/8 DAC channels, integrated PLL, no PGA on ADC inputs | Higher sample rate support but lacks programmable gain amplifier for low-level analog inputs | Preferred when ultra-high-resolution playback dominates over flexible analog input conditioning |
| CS42526-CQZ | 24-bit/192 kHz, 6 ADC/8 DAC, built-in jack detection, 1.8 V I/O support | Includes GPIO and jack sense logic; requires level-shifting for 5 V system integration | Selected for portable or battery-powered designs needing embedded control features and lower voltage operation |
Compared with AK4118VN and CS42526-CQZ, AD1836ACS offers unique A-weighted filter optimization and PGA configurability for mid-tier home theater and automotive systems where cost-sensitive analog signal conditioning is critical, without requiring 192 kHz capability or embedded microcontroller functions.
Availability
AD1836ACS is available at Aetrix Electronics and suitable for home theater receivers, automotive infotainment units, and DVD recorders requiring stable component supply, long-lifecycle availability, and consistent parametric performance across production batches.
Supply support for AD1836ACS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD1836A product line delivers multichannel audio codecs optimized for consumer and automotive entertainment systems, emphasizing low THD+N, flexible serial interfacing, and robust analog front-end design for real-world signal sources.
FAQ
What distinguishes AD1836ACS from AD1836AAS?
The AD1836ACS variant specifies A-weighted dynamic range of 97–102 dB (RMS) for ADCs, whereas AD1836AAS achieves 100–105 dB under identical conditions. This difference reflects process and trim variations within the same silicon family-both share identical pinout, register map, and functional capabilities. AD1836ACS remains fully compatible in all AD1836A-designated PCB layouts and firmware.
Does AD1836ACS support 96 kHz operation on all ADC channels?
No. AD1836ACS supports 96 kHz sampling only on the primary stereo ADC pair (ADC1L/R); the secondary ADC pair (ADC2L/R) operates at 48 kHz maximum. This limitation is inherent to the Σ-∆ modulator architecture and decimation filter configuration-confirmed in the Functional Overview section of the AD1836A datasheet Rev. 0.
Can AD1836ACS drive headphones directly?
No. AD1836ACS provides fully differential, current-output-capable DAC outputs (±1.4 V swing around 2.25 V common-mode) intended for connection to external op-amp-based low-pass filters and line drivers. It lacks integrated headphone amplifier circuitry, output current capability, or DC-blocking capacitors required for direct headphone loading.
How is the A-weighted filter implemented in AD1836ACS?
The A-weighted filter in AD1836ACS is a digital FIR filter applied post-decimation in the ADC signal path, enabled via SPI register configuration. It conforms to IEC 61672-1:2013 Class 1 weighting curve and operates exclusively in RMS measurement mode-no analog components or external parts are required to activate this function.
Is the SPI interface of AD1836ACS compatible with standard microcontrollers?
Yes. AD1836ACS implements a Motorola SPI-compatible 4-wire interface (CCLK, CLATCH, CDATA, COUT) with 16-bit command words and 8 MHz max clock rate. It operates asynchronously to audio clocks and supports standard CPOL=0, CPHA=0 timing-verified across STM32, PIC32, and NXP Kinetis families in reference designs.
AD1836ACS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- AD1836A
- Package/Case:
- 52-QFP
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Stereo Audio
- Data Interface:
- DSP, I2S, Serial, SPI
- Resolution (Bits):
- 16 b, 18 b, 20 b, 24 b
- Number of ADCs / DACs:
- 2 / 3
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 105 / 108
- Dynamic Range, ADCs / DACs (db) Typ:
- 105 / 108
- Voltage - Supply, Analog:
- 4.75V ~ 5.25V
- Voltage - Supply, Digital:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-MQFP (10x10)
AD1836ACS FAQ
1.How can I place an order for AD1836ACS through Aetrix?
Please submit a Request for Quotation (RFQ) for AD1836ACS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD1836ACS reliable?
The price and inventory of AD1836ACS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD1836ACS is usually 5 days.
3.What payment methods are accepted for AD1836ACS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD1836ACS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD1836ACS?
AD1836ACS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD1836ACS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD1836ACS?
For technical support, including AD1836ACS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD1836ACS requirements.
6.How does Aetrix verify that AD1836ACS is sourced from the original manufacturer or authorized distributors?
All AD1836ACS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD1836ACS meets industry standards.
7.What is the process for return or replacement of AD1836ACS?
All AD1836ACS units undergo pre-shipment inspection (PSI). If there is an issue with AD1836ACS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD1836ACS part is unused and in its original packaging.
Return procedure for AD1836ACS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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