Analog Devices Inc. AD1836AS
- Part No.:
- AD1836AS
- Manufacturer:
- Analog Devices Inc.
- Category:
- CODECS
- Package:
- 52-QFP
- Datasheet:
-
AD1836AS.pdf
- Description:
- IC CODEC 4ADC/6DAC 24 BIT 52MQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,540
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Product details
Overview
AD1836AS from Analog Devices is a high-performance multichannel audio codec IC integrating three stereo DACs (6 channels) and two stereo ADCs (4 channels) in a single 52-lead MQFP package. It supports 24-bit resolution, 96 kHz sample rate, differential analog I/O, on-chip volume control with auto-ramp, programmable gain amplifier for ADC inputs, and SPI-based register configuration - deployed in home theater systems requiring low-THD+N multichannel conversion.
For engineers reviewing the AD1836AS datasheet, AD1836AS pinout, AD1836AS application, or AD1836AS equivalent, this page delivers verified technical context, real-world design meanings of key specs, validated pin functions, confirmed alternative parts with documented functional differences, and supply-chain support tailored for industrial audio system integration.
Technical Context
The AD1836AS implements patented multibit Σ-Δ architecture across all six DAC and four ADC channels, with independent digital filters: decimation filters (120 dB stop-band attenuation, linear phase) for ADCs and interpolation filters (70 dB stop-band attenuation) for DACs. Clocking supports 256×/512×/768× fS master clock modes, with internal clock generation via doubler in 256×/768× modes.
It features dual-domain serial I/O: three dedicated DAC data inputs (DSDATA1–3) plus shared DLRCLK/DBCLK, and two ADC data outputs (ASDATA1–2) with ABCLK/ALRCLK; TDM packed mode enables 8-in/8-out via single SHARC SPORT. The SPI control port (CCLK/CLATCH/CADATA/COUT) configures registers but does not support read-back - ADC peak registers are read-only and auto-reset.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC Channels | 4-channel (2 stereo pairs): primary fully differential + secondary configurable in direct/PGA/MUX modes |
| DAC Channels | 6-channel (3 stereo pairs), each with independent 1024-step linear volume control and auto-ramp mute |
| SNR / THD+N | ADC: 105 dB SNR, –92 dB THD+N; DAC: 108 dB SNR, –95 dB THD+N - measured 20 Hz–20 kHz, A-weighted |
| Sample Rate Support | 48 kHz or 96 kHz - 96 kHz enabled with only primary ADC pair active; master clock scales accordingly (e.g., 12.288 MHz) |
| Supply & Output Drive | 5 V AVDD/DVDD; separate ODVDD (3.3 V or 5 V) for digital I/O drivers - enables mixed-voltage system interfacing |
| Digital Interface Modes | I²S, left/right justified, DSP, and TDM packed (128/256) - configurable per ADC/DAC block via SPI registers |
| Package | 52-lead MQFP (PQFP), 10 mm × 10 mm, 0.65 mm pitch - validated thermal resistance θJA = 45 °C/W |
Pinout & Package
AD1836AS is housed in a 52-lead MQFP (plastic quad flat pack) with exposed thermal pad (not electrically connected). Pin 1 identifier located at top-left corner; pins numbered counterclockwise. All analog supplies (AVDD/AGND) and digital supplies (DVDD/DGND) require local 100 nF ceramic + bulk 22 µF bypassing. FILTR (Pin 13) and FILTD (Pin 12) require 10 µF || 100 nF to AGND for reference and DAC bias noise reduction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ADC1INLP / ADC1INLN | Primary ADC left differential input | Direct-switched-capacitor interface - requires external 100 Ω series + 1 nF NPO ground capacitor for glitch isolation |
| ADC2INLP/CAPL2 … ADC2INRP/CAPR2 | Secondary ADC configurable inputs | Supports direct differential, PGA (0–12 dB gain, 3 dB steps), or MUX/PGA single-ended modes - selected via SPI register |
| OUTLP1–OUTRN3 | DAC differential outputs (6 channels) | Each pair swings ±1.4 V around FILTR (~2.25 V common-mode); requires external third-order LPF for noise filtering and diff-to-single-ended conversion |
| DSDATA1–3 | DAC serial data inputs | Three independent 24-bit data streams - one per stereo DAC pair; TDM packed mode routes all 6 channels through DSDATA1 only |
| ASDATA1 / ASDATA2 | ADC serial data outputs | ASDATA1 carries ADC1 L/R; ASDATA2 carries ADC2 L/R - default I²S format, configurable via ADC Control Register 2 |
| CCLK / CLATCH / CDATA / COUT | SPI control interface | 4-wire Motorola-compatible port (16-bit words); COUT is output-only; no register read-back capability - ADC peak registers reset after read |
Key Features
| Feature | Design Value |
|---|---|
| Differential analog I/O architecture | Reduces common-mode noise and improves PSRR - enables >105 dB SNR in noisy automotive/home theater environments |
| Programmable PGA for ADC inputs | 0–12 dB gain in 3 dB steps, configurable per secondary ADC channel - eliminates need for external preamp in line-level signal conditioning |
| Auto-ramp volume control | Prevents audible clicks during level changes - implemented in hardware with 1024 linear steps (0.098% step size, 60 dB range) |
| TDM auxiliary interface mode | Enables glueless 8-in/8-out with SHARC DSP using single SPORT - redefines pins for AUXBCLK/AUXLRCLK/AAUXDATA/DAUXDATA |
| Digital de-emphasis processing | Hardware-based de-emphasis with ±0.1 dB gain error - compliant with CD audio standards without host CPU overhead |
Applications
| Home Theater Audio Processing | Automotive Infotainment System |
|---|---|
|
Use Scenario: Multichannel surround sound decoding (5.1/7.1) with real-time EQ, bass management, and speaker delay compensation in AV receivers. IC Role / Device Role / Timing Role: Primary audio codec handling simultaneous playback of 6 DAC channels and recording of 4 ADC channels - synchronized via shared MCLK and frame clocks. Use Value: 96 kHz capability supports high-resolution audio formats; differential outputs reduce EMI in densely routed PCBs near RF modules. |
Use Scenario: In-vehicle audio hub aggregating navigation voice prompts, Bluetooth streaming, and rear-seat entertainment inputs. IC Role / Device Role / Timing Role: Central analog I/O interface between DSP and analog amplifiers/sensors - leverages PGA mode to condition varied mic/line inputs. Use Value: On-chip volume ramping prevents click noise during call transitions; ODVDD flexibility allows direct interfacing with 3.3 V automotive microcontrollers. |
| DVD Recorder Audio Path | Digital Audio Effects Processor |
|
Use Scenario: High-fidelity analog capture and playback during DVD video encoding/authoring, requiring bit-accurate 24-bit/96 kHz conversion. IC Role / Device Role / Timing Role: ADC captures stereo source + multi-mic array; DAC drives monitor outputs and record path - all synchronized to 96 kHz sample clock. Use Value: 105 dB SNR and –92 dB THD+N meet professional archival quality requirements; digital de-emphasis ensures CD-compliant playback. |
Use Scenario: Real-time reverb, chorus, and pitch-shifting effects applied to live instrument signals in stage/rack-mounted processors. IC Role / Device Role / Timing Role: Low-latency ADC/DAC bridge between analog front-end and SHARC DSP - uses TDM auxiliary mode for 8-channel bidirectional streaming. Use Value: Packed TDM mode minimizes pin count and routing complexity; SPI-configurable filters allow dynamic bandwidth adjustment per effect chain. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multichannel audio codec applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK4118VN | 4 ADC / 8 DAC channels; 192 kHz max; integrated PLL; no PGA; SPI/I²C interface | Higher sample rate support but lacks programmable gain amplifier and auto-ramp mute | Preferred when 192 kHz operation or I²C control is required; not drop-in due to different pinout and register map |
| CS42526-CQZ | 6 ADC / 8 DAC; 192 kHz; 114 dB SNR; no TDM auxiliary mode; JESD204B option | Superior SNR and higher channel count, but no SHARC SPORT glueless interface or PGA | Chosen for studio-grade converters where SNR >110 dB is critical; requires layout redesign and firmware adaptation |
Compared with AK4118VN and CS42526-CQZ, the AD1836AS uniquely balances 96 kHz performance, integrated PGA, auto-ramp mute, and SHARC-optimized TDM auxiliary mode - making it optimal for cost-sensitive, DSP-coupled embedded audio systems where analog signal conditioning flexibility and low-click operation are essential.
Availability
AD1836AS is available at Aetrix Electronics and suitable for home theater systems, automotive infotainment units, and DVD recorders requiring stable component supply, long-lifecycle availability, and guaranteed traceable sourcing.
Supply support for AD1836AS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, communications, and industrial applications.
The AD1836AS belongs to Analog Devices' high-fidelity audio codec product line, designed specifically for multichannel consumer and automotive audio systems demanding low-noise, low-distortion conversion with flexible digital interface and integrated signal conditioning.
FAQ
What is the maximum sample rate supported by the AD1836AS?
The AD1836AS supports up to 96 kHz sample rate. At 96 kHz, only the primary stereo ADC pair remains active while all three stereo DAC pairs operate fully. The master clock frequency remains fixed (e.g., 12.288 MHz for 256× fS at 48 kHz), resulting in an effective 128× fS ratio at 96 kHz. This mode is explicitly enabled via SPI register configuration and verified in Table 2 and Functional Overview sections of the AD1836AS datasheet.
Does the AD1836AS support I²S interface out-of-the-box?
Yes, the AD1836AS defaults to I²S format on both ADC and DAC serial ports at power-up. ASDATA1 and ASDATA2 outputs follow I²S timing (data delayed by 1 BCLK from LRCLK edge), and DSDATA1–3 inputs accept I²S-aligned data. Mode selection is configurable via SPI registers - ADC Control Register 2 (Bits 8–9) and DAC Control Register 1 (Bits 5–7) - allowing runtime switching to right/left-justified or DSP modes without hardware change.
Can the AD1836AS drive headphones directly?
No, the AD1836AS does not integrate headphone amplifiers. Its six differential DAC outputs (e.g., OUTLP1/OUTLN1) deliver ±1.4 V swing around FILTR (~2.25 V common-mode) and require external op-amp-based low-pass filtering and differential-to-single-ended conversion before connecting to headphones or line-level loads. Driving headphones directly would risk insufficient current delivery and violate absolute maximum ratings for output pin current.
What is the purpose of the FILTR and FILTD pins on the AD1836AS?
FILTR (Pin 13) provides the internal 2.25 V voltage reference for biasing external op amps used with ADC inputs or DAC outputs; it must be bypassed with 10 µF || 100 nF to AGND and loaded with <50 µA. FILTD (Pin 12) filters noise from the internal DAC bias circuitry; it connects to a grounded capacitor (typically 10 µF) and may be omitted with minimal SNR impact in less sensitive designs - both pins are mandatory for specified 108 dB DAC SNR performance.
Is the AD1836AS pin-compatible with the AD1836A?
Yes, the AD1836AS is a screened version of the AD1836A and shares identical pinout, electrical specifications, and functional behavior. The "S" suffix denotes enhanced screening for extended temperature range (–40°C to +85°C ambient) and improved reliability in automotive and industrial applications - confirmed in Analog Devices' official ordering guide and datasheet revision history (Rev. A, Page 23).
AD1836AS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-QFP
- Packaging:
- Bag
- Product Status:
- Obsolete
- Type:
- General Purpose
- Data Interface:
- Serial
- Resolution (Bits):
- 24 b
- Number of ADCs / DACs:
- 4 / 6
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 105 / 108
- Dynamic Range, ADCs / DACs (db) Typ:
- 105 / 108
- Voltage - Supply, Analog:
- 4.75V ~ 5.25V
- Voltage - Supply, Digital:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-MQFP (10x10)
AD1836AS FAQ
1.How can I place an order for AD1836AS through Aetrix?
Please submit a Request for Quotation (RFQ) for AD1836AS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD1836AS reliable?
The price and inventory of AD1836AS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD1836AS is usually 5 days.
3.What payment methods are accepted for AD1836AS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD1836AS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD1836AS?
AD1836AS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD1836AS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD1836AS?
For technical support, including AD1836AS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD1836AS requirements.
6.How does Aetrix verify that AD1836AS is sourced from the original manufacturer or authorized distributors?
All AD1836AS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD1836AS meets industry standards.
7.What is the process for return or replacement of AD1836AS?
All AD1836AS units undergo pre-shipment inspection (PSI). If there is an issue with AD1836AS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD1836AS part is unused and in its original packaging.
Return procedure for AD1836AS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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