Analog Devices Inc. AD1879JD
- Part No.:
- AD1879JD
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-CDIP (0.605", 15.37mm)
- Datasheet:
-
AD1879JD.pdf
- Description:
- 18-BIT SIGMA DELTA STEREO ADC
- Quantity:
- Payment:

- Shipping:

Inventory:671
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Product details
Overview
AD1879JD from Analog Devices is an 18-bit, dual-channel, sigma-delta stereo analog-to-digital converter (ADC) designed for high-fidelity digital audio systems. It features fully differential analog inputs, 103 dB typical SNR, –98 dB THD+N, and a single-stage 4095-tap FIR decimation filter. It operates with ±5 V supplies over –25°C to +70°C and targets professional audio digitization at 44.1 kHz or 48 kHz sampling rates.
For engineers reviewing the AD1879JD datasheet, AD1879JD pinout, AD1879JD application, or AD1879JD equivalent, key selection considerations include its 18-bit resolution, 256×FS master clock requirement, differential input architecture, on-chip voltage reference, and ceramic DIP-28 package with isolated analog/digital supply domains.
Technical Context
The AD1879JD implements a proprietary fifth-order, single-bit switched-capacitor sigma-delta modulator per channel, oversampling at 64×FS and shaping quantization noise beyond the audio band. Its modulator output feeds a symmetric, linear-phase, 4095-tap FIR decimator that reduces data rate to FS while delivering <0.001 dB passband ripple and >115 dB stopband attenuation.
Digital interface flexibility includes master/slave mode selection via S0/S1 pins, programmable frame formats (I²S-compatible, right-justified), and 32-bit or 16-bit word-length output. The device integrates separate BiCMOS (modulator/reference) and CMOS (decimator/interface) die in one ceramic DIP-28 package to minimize digital crosstalk.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit - delivers full 18-bit dynamic range without dithering dependency; supports 20 kHz audio bandwidth with 115 dB stopband rejection. |
| Dynamic Range (Stereo, no A-weight) | 103 dB typ - enables recording of low-level signals (e.g., ambient room tone at –60 dBFS) above integrated noise floor in 0–20 kHz band. |
| THD+N (Full Scale) | –98 dB typ - ensures minimal harmonic and noise distortion in line-level professional audio signal paths. |
| Decimation Filter | Single-stage 4095-tap FIR - provides linear phase, group delay of 32/FS (667 µs @ 48 kHz), and eliminates need for external analog antialiasing beyond simple RC. |
| Input Clock Range | 12.288 MHz (48 kHz FS) to 14.286 MHz - supports standard audio sample rates including 44.1 kHz (11.2896 MHz) and 32 kHz (8.192 MHz). |
| Analog Input | Fully differential ±6.3 V range - rejects common-mode noise and enables >100 dB CMRR; requires no external sample-and-hold. |
| Supply Voltages | ±5 V (AVDD1/AVSS1, AVDD2/AVSS2, DVDD) - separates analog core, analog logic, and digital domains to suppress supply-induced crosstalk. |
Pinout & Package
Ceramic Dual In-line Package (DIP-28), 0.600" wide, with 0.100" lead pitch. Pin 1 index located at top-left corner when viewed from top with notch up. Analog and digital grounds are physically separated; AVSS1/AVSS2 and AVDD1/AVDD2 are dedicated to analog sections, DVDD/DGND to digital section.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–10, 18–23 | Analog & Digital Supply/Ground | Isolated AVDD1/AVSS1 (core analog), AVDD2/AVSS2 (analog logic), DVDD/DGND (digital) - prevents supply coupling between domains. |
| 11 | APD | Active-HI analog power-down control - reduces analog current from 92 mA to 23 mA; preserves digital interface functionality. |
| 12–13, 16–17, 27–28 | Audio Interface | VINL±/VINR± (differential inputs), REFL/REFR (reference caps), LRCK/BCK/WCK/DATA (serial output) - support I²S, right-justified, or custom framing. |
| 14–15, 24–26 | Configuration & Timing | 64/32 (bit-rate select), S0/S1 (mode), RESET (sync initialization), CLOCK (256×FS master clock) - enable flexible system integration and multi-device synchronization. |
| 17 | NC | No connection - must remain unconnected; internal node not bonded out. |
Key Features
| Feature | Design Value |
|---|---|
| Fifth-order differential sigma-delta modulator | Shapes quantization noise >100 dB above 20 kHz, enabling simple antialias filtering and eliminating idle tones below –110 dBFS. |
| On-chip 3 V voltage reference | Stable over temperature (150 ppm/°C gain drift); buffers both channels to minimize interchannel gain mismatch (<0.15 dB). |
| Single-stage 4095-tap FIR decimator | Delivers linear phase, 0.001 dB passband ripple, and >115 dB stopband attenuation without multiplier hardware - reduces silicon area and power vs. multistage designs. |
| Fully differential analog inputs | ±6.3 V input range with 7 kΩ input impedance per pin - achieves >103 dB SNR and >100 dB crosstalk by rejecting board-level EMI and ground bounce. |
| Separate BiCMOS/CMOS die integration | BiCMOS modulator + reference + CMOS decimator/interface in one DIP-28 - isolates sensitive analog nodes from digital switching noise at layout level. |
Applications
| Digital Audio Tape (DAT) Recorder | Professional Sound Reinforcement System |
|---|---|
Use Scenario: High-resolution analog input capture from microphone preamps or line sources before digital mixing and storage. IC Role / Device Role / Timing Role: Primary stereo ADC converting balanced XLR or TRS inputs to time-multiplexed serial digital output synchronized to AES/EBU or I²S clocks. Use Value: 103 dB SNR and –98 dB THD+N preserve transient detail and low-level ambience critical for archival-quality tape duplication. | Use Scenario: Front-end digitization of live stage signals prior to DSP-based equalization, dynamics processing, and networked distribution. IC Role / Device Role / Timing Role: Dual-channel ADC providing low-latency, low-jitter conversion with deterministic group delay (667 µs @ 48 kHz) for real-time feedback control. Use Value: Fully differential inputs reject common-mode noise from long cable runs and dimmer-induced EMI in venue power systems. |
| CD-R Mastering Equipment | A/V Digital Amplifier Input Stage |
Use Scenario: Precision analog-to-digital conversion of studio master tapes or DAW outputs for CD premastering and Red Book compliance verification. IC Role / Device Role / Timing Role: Reference-grade ADC operating at 44.1 kHz FS with 256× master clock (11.2896 MHz) and I²S-compatible output framing. Use Value: <0.001 dB passband ripple and linear-phase FIR filter prevent audible coloration during spectral analysis and bit-perfect replication. | Use Scenario: Digitizing analog audio inputs (e.g., phono, line, tuner) in Class-D amplifier platforms with integrated DSP and DAC playback. IC Role / Device Role / Timing Role: Stereo ADC feeding internal DSP engine; uses APD pin for power-gating during standby to reduce system quiescent current. Use Value: On-chip 3 V reference and trimmed THD+N performance ensure consistent gain calibration across production units without external trimming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar stereo audio ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK5355VT | 24-bit, 128× oversampling, integrated analog front-end; requires external 1.8 V/3.3 V supplies; no ±5 V analog rails. | Targets portable battery-powered recorders; lacks ±5 V analog compatibility and ceramic DIP-28 footprint. | Select AK5355VT only if migrating to lower-voltage, higher-resolution, surface-mount design with revised power architecture. |
| CS5361-KQZ | 24-bit, delta-sigma, 128× oversampling; supports 3.3 V digital I/O; no internal voltage reference - requires external 2.5 V ref. | Designed for consumer A/V receivers; lacks on-chip reference stability and ±5 V analog supply tolerance. | Choose CS5361-KQZ when prioritizing 24-bit resolution and cost-sensitive volume production over legacy ±5 V compatibility and reference autonomy. |
Compared with AK5355VT and CS5361-KQZ, the AD1879JD offers unique value in legacy professional audio systems requiring ±5 V operation, autonomous 3 V reference, ceramic DIP-28 reliability, and guaranteed 103 dB SNR without external trimming - making it irreplaceable for repair, recalibration, and drop-in replacement in installed base equipment.
Availability
AD1879JD is available at Aetrix Electronics and suitable for digital tape recorders, professional sound reinforcement systems, CD-R mastering equipment, and A/V digital amplifier input stages requiring stable component supply and long-term obsolescence management.
Supply support for AD1879JD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, industrial, and audio applications.
The AD1879JD belongs to Analog Devices' high-fidelity audio ADC product line, engineered specifically for professional digital audio acquisition where SNR, THD+N, and analog integrity outweigh raw bit depth - emphasizing robustness in ±5 V systems and legacy DIP packaging.
FAQ
What is the maximum supported sampling frequency for AD1879JD?
The AD1879JD supports output word rates (FS) up to 55.8 kHz, corresponding to a master clock (CLOCK) input of 14.286 MHz (256 × FS). At 48 kHz FS, the required CLOCK frequency is 12.288 MHz - the most commonly used configuration in professional audio gear. Operation beyond 55.8 kHz FS is not specified and may result in degraded SNR or timing violations.
Does AD1879JD require external voltage reference components?
No, the AD1879JD includes an internal 3 V voltage reference buffered to both analog channels. External 10 µF tantalum capacitors must be connected to REFL (Pin 15) and REFR (Pin 14) for stability, but no external reference IC is needed. An external reference can override the internal one only if applied directly to those pins - otherwise, the AD1879JD operates autonomously.
Can AD1879JD operate with a 3.3 V digital supply instead of 5 V?
No, the AD1879JD requires DVDD = +5 V (4.75–5.25 V) and AVDD1/AVDD2 = +5 V (4.75–5.25 V) per its Absolute Maximum Ratings and DC specifications. Its digital inputs (VIH = 2.0 V min, VIL = 0.8 V max) are TTL/CMOS-compatible but not 3.3 V–optimized; using 3.3 V DVDD risks violating VIH thresholds and causing unreliable serial interface operation.
How does the APD pin affect AD1879JD functionality during power-down mode?
When APD (Pin 11) is driven HIGH, the AD1879JD disables its analog modulators and reference, reducing analog supply current from 92 mA to 23 mA. The digital interface remains active: CLOCK, RESET, and serial output continue functioning, but DATA output becomes invalid. This allows system-level power gating without disrupting clock distribution or requiring full device reset.
Is AD1879JD pin-compatible with AD1878JD?
Yes, AD1879JD and AD1878JD share identical pinout, package (ceramic DIP-28), supply requirements, and interface timing. The only functional difference is resolution: AD1879JD outputs 18-bit words, while AD1878JD outputs 16-bit words. Both accept the same 256×FS master clock and support identical serial framing modes - enabling direct substitution where 18-bit resolution is not required.
AD1879JD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- AD1879
- Package/Case:
- 28-CDIP (0.605", 15.37mm)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- -
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- Serial
- Configuration:
- ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Sigma-Delta
- Reference Type:
- External
- Voltage - Supply, Analog:
- -5.25V ~ -4.75V, 4.75V ~ 5.25V
- Voltage - Supply, Digital:
- -5.25V ~ -4.75V, 4.75V ~ 5.25V
- Features:
- -
- Operating Temperature:
- -25°C ~ 70°C
- Supplier Device Package:
- 28-CDIP
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
AD1879JD FAQ
1.How can I place an order for AD1879JD through Aetrix?
Please submit a Request for Quotation (RFQ) for AD1879JD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD1879JD reliable?
The price and inventory of AD1879JD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD1879JD is usually 5 days.
3.What payment methods are accepted for AD1879JD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD1879JD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD1879JD?
AD1879JD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD1879JD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD1879JD?
For technical support, including AD1879JD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD1879JD requirements.
6.How does Aetrix verify that AD1879JD is sourced from the original manufacturer or authorized distributors?
All AD1879JD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD1879JD meets industry standards.
7.What is the process for return or replacement of AD1879JD?
All AD1879JD units undergo pre-shipment inspection (PSI). If there is an issue with AD1879JD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD1879JD part is unused and in its original packaging.
Return procedure for AD1879JD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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