Analog Devices Inc. AD1928YSTZ
- Part No.:
- AD1928YSTZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- CODECS
- Package:
- 48-LQFP
- Datasheet:
-
AD1928YSTZ.pdf
- Description:
- IC CODEC 2ADC 8DAC W/PLL 48LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD1928YSTZ from Analog Devices is a 2-channel ADC / 8-channel DAC high-performance audio codec IC with integrated PLL, 24-bit resolution, 192 kHz sample rate support, and 108 dB DAC dynamic range. It operates from a single 3.3 V supply, features differential ADC inputs and single-ended DAC outputs, and targets multichannel automotive audio systems requiring low-EMI clocking and flexible digital audio interface.
For engineers reviewing the AD1928YSTZ datasheet, AD1928YSTZ pinout, AD1928YSTZ application, or AD1928YSTZ equivalent, this page delivers verified technical context, real-world timing and filtering behavior, SPI-controllable volume/autoramp/mute functions, and precise package-level design meaning for LQFP-48 layout integration.
Technical Context
The AD1928YSTZ implements Analog Devices' patented multibit sigma-delta architecture for both ADCs and DACs, with on-chip digital antialiasing (79 dB stop-band attenuation) and reconstruction filters (70 dB stop-band attenuation). Its PLL supports 256×/384×/512×/768× fS multiplication from MCLKI/XI or LRCLK, enabling master clock derivation without external high-frequency sources.
Dual stereo ADCs accept differential inputs with 1.5 V common-mode bias and internal high-pass filtering (1.4 Hz cutoff at 48 kHz); eight single-ended DAC outputs each provide independent 0.375 dB log-volume control across 95 dB range. Serial interfaces include SPI (24-bit words), four DAC data inputs (DSDATA1–4), two ADC data outputs (ASDATA1, ADCTDMOUT), and TDM-capable clock domains supporting up to 16 channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC/DAC Channels | 2 ADC (differential input), 8 DAC (single-ended output) - enables stereo capture + 4-zone playback in compact audio subsystems |
| Resolution & Sample Rate | 24-bit, 8–192 kHz - supports CD, DVD-Audio, and high-res streaming formats with scalable oversampling (128× for ADC, 4×/2× for DAC) |
| DAC Dynamic Range | 108 dB (A-weighted, RMS) - achieves studio-grade noise floor for premium automotive infotainment |
| THD + N | −94 dB (DAC, 0 dBFS, 8-channel active) - ensures clean multi-channel output without intermodulation distortion |
| Supply Voltage | 3.3 V ±10% (AVDD/DVDD) - simplifies power design with single rail and tolerance for 5 V logic inputs |
| PLL Clock Flexibility | 256×/384×/512×/768× fS modes with LRCLK or crystal reference - eliminates need for external 12.288 MHz oscillator in 48 kHz systems |
| Interface Support | SPI control port + I²S/TDM/Right-justified/Left-justified serial formats - allows direct connection to DSPs, SoCs, or FPGA audio controllers |
Pinout & Package
AD1928YSTZ is housed in a 48-lead LQFP package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are validated per Rev. B datasheet Figure 2 and Table 10. Analog and digital grounds are segregated; AVDD appears on pins 5, 33, 37, 48; DVDD on pin 13; AGND on pins 1, 4, 32, 34, 36.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ADC1LP / ADC1LN / ADC1RP / ADC1RN | Differential analog input pair (stereo) | Accepts balanced line-level signals; requires 100 Ω series + 1 nF shunt RC filter per input for optimal SNR |
| OL1–OL4 / OR1–OR4 | Single-ended DAC analog outputs (4 stereo pairs) | Each swings ±1.27 V around 1.5 V CM level; needs external third-order LPF to suppress out-of-band noise |
| MCLKI/XI & MCLKO/XO | Crystal oscillator input/output or master clock I/O | Enables crystal-based clock generation (no external oscillator needed) or accepts 6.9–27.6 MHz reference |
| PD/RST | Active-low power-down/reset | Pulls all registers to defaults; analog outputs remain active during reset to prevent pop/click artifacts |
| CIN / COUT / CCLK / CLATCH | SPI control interface | 24-bit command protocol; CLATCH must be pulled up externally to detect microcontroller presence in standalone mode |
| FILTR & CM | Voltage reference filter and common-mode bias | FILTR requires 10 μF||100 nF to AGND; CM supplies 1.5 V bias for external op-amp input/output buffering |
Key Features
| Feature | Design Value |
|---|---|
| Low-EMI architecture | On-chip PLL eliminates external high-frequency master clock; continuous-time sigma-delta converters minimize switching noise coupling |
| Logarithmic volume control | 255-step, 0.375 dB/step attenuation per DAC channel with autoramp - prevents zipper noise during real-time gain changes |
| Clickless mute | Software-controlled zero-crossing mute activation - avoids transient spikes during muting/unmuting in live audio paths |
| TDM scalability | Supports up to 16-channel I/O on shared DBCLK/ABCLK lines - reduces PCB trace count in multi-zone automotive head units |
| Differential ADC input | 100 kΩ input impedance, 55 dB CMRR at 20 kHz - rejects engine noise and RF interference in vehicle environments |
Applications
| Automotive Infotainment Head Unit | Home Theater AV Receiver |
|---|---|
Use Scenario: Central audio processor handling navigation voice prompts, Bluetooth streaming, and rear-seat entertainment simultaneously. IC Role / Device Role / Timing Role: AD1928YSTZ acts as primary audio codec, converting DSP-generated digital streams to analog outputs for 4-zone amplification while digitizing microphone inputs for echo cancellation. Use Value: 108 dB DAC dynamic range preserves dialog clarity; TDM mode consolidates 8 DAC channels onto two serial buses, reducing routing complexity on dense automotive PCBs. |
Use Scenario: High-fidelity 7.1-channel surround sound system decoding Dolby TrueHD and DTS-HD Master Audio. IC Role / Device Role / Timing Role: AD1928YSTZ serves as front-end DAC for left/right main channels and rear/surround zones, synchronized via shared LRCLK and DBCLK under I²S format. Use Value: −94 dB THD+N at full 8-channel load ensures distortion-free playback at reference listening levels; 192 kHz capability supports future-proof high-resolution content rendering. |
| Digital Audio Effects Processor | Set-Top Box Audio Subsystem |
Use Scenario: Real-time reverb, equalization, and bass management applied to HDMI audio before analog output to legacy TVs or soundbars. IC Role / Device Role / Timing Role: AD1928YSTZ receives processed PCM from FPGA, applies final volume scaling and mute control, then drives line outputs with minimal latency. Use Value: SPI-controllable autoramp enables smooth parameter sweeps during effect transitions; 3.3 V operation matches FPGA I/O voltage, eliminating level shifters. |
Use Scenario: Compact set-top box delivering stereo analog audio alongside HDMI video, with support for Dolby Digital passthrough and analog downmix. IC Role / Device Role / Timing Role: AD1928YSTZ handles dual-role conversion: digitizing IR remote audio feedback and converting decoded AC-3 bitstream to analog L/R outputs. Use Value: Differential ADC input rejects noise from nearby switching power supplies; 5 V-tolerant digital inputs simplify interface with legacy STB SoCs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar audio codec applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK4621VN | 2 ADC / 6 DAC, 24-bit/192 kHz, 102 dB DR, 3.3 V only, no integrated PLL | Lacks on-chip PLL and two DAC channels; requires external clock generator and cannot support 4-zone output without additional DACs | Choose when lower channel count suffices and external clocking is already available; not suitable for space-constrained automotive modules needing self-contained timing. |
| CS42888-CQZ | 4 ADC / 8 DAC, 24-bit/192 kHz, 114 dB DR, 3.3 V/5 V dual-supply, integrated PLL | Higher ADC count and dynamic range but larger 64-pin QFN package; supports 5 V I/O natively without level translation | Prefer for designs requiring quad-mic input (e.g., far-field voice assistant) or where 5 V logic compatibility is mandatory; AD1928YSTZ offers smaller footprint and lower EMI in 48-pin LQFP. |
Compared with AK4621VN and CS42888-CQZ, AD1928YSTZ uniquely balances 8-DAC channel density, PLL-integrated low-EMI clocking, and 48-pin LQFP packaging-making it optimal for cost-sensitive, space-limited automotive and consumer audio where full 4-zone playback and robust noise immunity are required.
Availability
AD1928YSTZ is available at Aetrix Electronics and suitable for automotive infotainment systems, home theater receivers, and digital audio effects processors requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.
Supply support for AD1928YSTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with deep expertise in precision data conversion and audio technology.
The AD1928YSTZ belongs to Analog Devices' high-fidelity audio codec product line, engineered specifically for automotive and premium consumer audio applications demanding low EMI, wide dynamic range, and flexible digital interface support in compact packages.
FAQ
What is the maximum sample rate supported by the AD1928YSTZ?
The AD1928YSTZ supports sample rates from 8 kHz up to 192 kHz across all ADC and DAC channels. At 192 kHz, the DAC interpolation filter operates at 128× oversampling, and the ADC decimation filter maintains 79 dB stop-band attenuation. This capability enables high-resolution audio playback and recording in professional and automotive applications where fidelity is critical. The AD1928YSTZ retains full 24-bit resolution and specified dynamic range (108 dB DAC, 107 dB ADC) at the top end of its operating range.
Does the AD1928YSTZ require an external crystal oscillator?
No-the AD1928YSTZ includes an on-chip PLL that can generate internal clocks from either an external crystal connected to MCLKI/XI and MCLKO/XO pins or from the LRCLK signal. When using a crystal, a parallel resonant fundamental-mode crystal (e.g., 12.288 MHz for 48 kHz systems) is recommended. The PLL eliminates the need for a separate high-frequency oscillator, reducing BOM cost and board space. The AD1928YSTZ also accepts direct master clock inputs up to 27.6 MHz if external timing is preferred.
How many independent volume controls does the AD1928YSTZ provide?
The AD1928YSTZ provides eight independent logarithmic volume controls-one per DAC channel-with 255 programmable steps at 0.375 dB increments and a total range of 95 dB. Each channel's attenuation is controlled via SPI-accessible DAC Control Registers. The device also includes autoramp functionality, which automatically ramps volume changes over programmable time intervals to eliminate audible zipper noise during real-time adjustments. This feature is implemented entirely within the AD1928YSTZ and requires no host-side interpolation.
Can the AD1928YSTZ operate with 5 V logic signals?
Yes-the AD1928YSTZ tolerates 5 V logic inputs on all digital pins (CIN, COUT, CCLK, CLATCH, DSDATAx, DBCLK, DLRCLK, ASDATA1, ABCLK, ALRCLK, PD/RST), while operating from a 3.3 V supply. This allows direct interfacing with legacy 5 V microcontrollers or FPGAs without level-shifting circuitry. However, output pins (COUT, DSDATAx, ASDATA1, ADCTDMOUT) are 3.3 V CMOS and must not drive 5 V-tolerant inputs without appropriate buffering or clamping if those inputs lack 3.3 V compatibility.
What is the purpose of the FILTR and CM pins on the AD1928YSTZ?
The FILTR pin connects to an external 10 μF||100 nF capacitor to AGND and stabilizes the internal 1.5 V reference voltage used by the ADC and DAC circuits. The CM pin provides a buffered 1.5 V common-mode reference output, intended to bias external op-amps used for ADC input conditioning or DAC output filtering. Both pins are essential for achieving datasheet-specified dynamic range and THD+N performance; omitting the FILTR capacitor degrades SNR by >3 dB, and floating CM introduces gain error and increased crosstalk in differential input stages.
AD1928YSTZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Type:
- General Purpose
- Data Interface:
- Serial
- Resolution (Bits):
- 24 b
- Number of ADCs / DACs:
- 2 / 8
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 94 / 94
- Dynamic Range, ADCs / DACs (db) Typ:
- 105 / 108
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LQFP (7x7)
AD1928YSTZ FAQ
1.How can I place an order for AD1928YSTZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD1928YSTZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD1928YSTZ reliable?
The price and inventory of AD1928YSTZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD1928YSTZ is usually 5 days.
3.What payment methods are accepted for AD1928YSTZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD1928YSTZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD1928YSTZ?
AD1928YSTZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD1928YSTZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD1928YSTZ?
For technical support, including AD1928YSTZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD1928YSTZ requirements.
6.How does Aetrix verify that AD1928YSTZ is sourced from the original manufacturer or authorized distributors?
All AD1928YSTZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD1928YSTZ meets industry standards.
7.What is the process for return or replacement of AD1928YSTZ?
All AD1928YSTZ units undergo pre-shipment inspection (PSI). If there is an issue with AD1928YSTZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD1928YSTZ part is unused and in its original packaging.
Return procedure for AD1928YSTZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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