Analog Devices Inc. AD5590BBCZ

Overview

AD5590BBCZ from Analog Devices is a 16-input/16-output analog I/O port IC integrating a 12-bit SAR ADC, sixteen 12-bit DACs, and eight rail-to-rail operational amplifiers - all operating from a single 4.5 V to 5.25 V supply. It delivers 1 MSPS ADC throughput, on-chip 2.5 V reference, hardware LDAC/CLR control, and SPI/QSPI/MICROWIRE-compatible serial interface. Used in optical line cards and base station monitoring systems for synchronized analog signal acquisition and generation.

For engineers reviewing the AD5590BBCZ datasheet, AD5590BBCZ pinout, AD5590BBCZ application, or AD5590BBCZ equivalent, this page provides verified functional architecture, real-world timing constraints (e.g., 800 ns ADC conversion time), amplifier offset voltage (2.2 mV max), DAC settling time (10 µs), and validated alternative part selection guidance - all grounded in Rev. A datasheet specifications.

Technical Context

The AD5590BBCZ integrates three independent functional blocks: a sequencer-controlled 16-channel 12-bit SAR ADC with 70 dB SNR at 50 kHz input, two groups of eight 12-bit string DACs each with dedicated internal references (VREFIN1/VREFOUT1 and VREFIN2/VREFOUT2), and eight low-noise op amps (22 nV/√Hz, 1 pA input bias) usable for ADC front-end conditioning or DAC output buffering. All blocks share a unified serial interface but operate with separate power domains (ADCVDD/ADCGND, DACVDD/DACGND, VDRIVE).

ADC conversion is initiated by ASYNC falling edge and clocked by ASCLK (up to 20 MHz), with no pipeline delay; DAC updates are controlled via DSYNC1/DSYNC2 framing and LDAC-synchronized register latching. The device supports dual reference modes (internal 2.5 V ±10 ppm/°C or external), programmable input range (0–VREFA or 0–2×VREFA), and asynchronous CLR to zero/midscale/full-scale code across all DACs.

Key Specifications

Pinout & Package

AD5590BBCZ is housed in an 80-ball CSP_BGA package (5.0 mm × 5.0 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are fully defined in Analog Devices Rev. A datasheet Figure 5 and Table 10, including dual-domain grounding (ADCGND and DACGND), separate analog/digital supplies (ADCVDD, DACVDD, VDRIVE), and dedicated frame sync lines (ASYNC, DSYNC1, DSYNC2) for independent ADC/DAC group control.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog I/O port applications.

Compared with AD7606C-16 and MAX11300, the AD5590BBCZ uniquely combines matched 16-in/16-out resolution, integrated amplifiers, and hardware-synchronized update logic - making it the only single-package solution for telecom-grade closed-loop analog control requiring simultaneous I/O and sub-microsecond determinism.

Availability

AD5590BBCZ is available at Aetrix Electronics and suitable for optical line cards, base station RF calibration, and industrial process controllers requiring stable component supply across extended product lifecycles.

Supply support for AD5590BBCZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD5590BBCZ belongs to Analog Devices' precision analog I/O portfolio, designed specifically for telecom infrastructure and industrial automation systems demanding tightly coupled ADC/DAC synchronization, integrated signal conditioning, and robust operation across −40°C to +85°C.

FAQ

What is the maximum ADC sampling rate supported by the AD5590BBCZ?

The AD5590BBCZ achieves a maximum throughput rate of 1 MSPS under specified conditions (ADCVDD = 4.75 V to 5.25 V, ASCLK = 20 MHz). This is enabled by its 12-bit successive approximation architecture with no pipeline delay - each conversion completes in exactly 800 ns, allowing deterministic timing for real-time control loops. The AD5590BBCZ datasheet Rev. A confirms this value in Table 1 under "CONVERSION RATE".

Does the AD5590BBCZ include an internal voltage reference for both ADC and DAC sections?

Yes, the AD5590BBCZ integrates an on-chip 2.5 V reference used by the ADC section (VREFA) and provides two independent reference outputs (VREFIN1/VREFOUT1 and VREFIN2/VREFOUT2) for the DAC groups. These internal references are disabled at power-up to allow external reference use and are enabled via software writes. The AD5590BBCZ reference exhibits ±10 ppm/°C drift and 2.495 V to 2.505 V tolerance at ambient, as specified in Table 2.

How many operational amplifiers are integrated into the AD5590BBCZ, and what are their key electrical characteristics?

The AD5590BBCZ integrates eight rail-to-rail operational amplifiers. Key confirmed specs include: offset voltage ≤2.2 mV (max), input bias current ≤1 pA (max), voltage noise density = 22 nV/√Hz at 10 kHz, and unity-gain stability. These amplifiers are intended for signal conditioning of ADC inputs, DAC outputs, or independent circuitry - and are fully characterized across −40°C to +85°C per Table 4 in the AD5590BBCZ datasheet Rev. A.

Can the AD5590BBCZ perform simultaneous updates across all 16 DAC outputs?

Yes, the AD5590BBCZ supports true simultaneous DAC output updates via its hardware LDAC pin. When LDAC is pulsed low, all 16 DAC outputs update in unison from their respective input registers - eliminating inter-channel skew. This function operates independently of the serial interface and is guaranteed to complete within 10 µs settling time (¼ to ¾ scale), as documented in Table 3 of the AD5590BBCZ datasheet.

What package type and pin count does the AD5590BBCZ use?

The AD5590BBCZ uses an 80-ball CSP_BGA package (5.0 mm × 5.0 mm, 0.5 mm pitch) with exposed thermal pad. Pin configuration is fully detailed in Figure 5 and Table 10 of the AD5590BBCZ Rev. A datasheet, including dual ground domains (ADCGND and DACGND), separate supply pins (ADCVDD, DACVDD, VDRIVE), and dedicated frame sync lines (ASYNC, DSYNC1, DSYNC2) for independent ADC/DAC group control.