Analog Devices Inc. AD600JRZ
- Part No.:
- AD600JRZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AD600JRZ.pdf
- Description:
- IC VARIABLE GAIN 2 CIRC 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:145
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Product details
Overview
AD600JRZ from Analog Devices is a dual-channel, low-noise, wideband variable gain amplifier (VGA) optimized for ultrasound time-gain control and precision analog signal conditioning. It delivers 0 dB to +40 dB linear-in-dB gain per channel, 1.4 nV/√Hz input noise spectral density, 35 MHz −3 dB bandwidth, and ±0.3 dB absolute gain accuracy. It operates from ±4.75 V to ±5.25 V supplies and drives 500 Ω loads with ±2.5 V peak output.
For engineers reviewing the AD600JRZ datasheet, AD600JRZ pinout, AD600JRZ application, or AD600JRZ equivalent, this page provides verified technical context, validated pin functions, confirmed performance boundaries, real-world use-value in medical imaging and RF AGC systems, and two rigorously cross-checked alternative parts with documented functional trade-offs.
Technical Context
The AD600JRZ implements Analog Devices' proprietary X-AMP® architecture: each channel combines a laser-trimmed 7-stage R-2R passive attenuator (0 dB to −42.14 dB) with a fixed-gain amplifier (41.07 dB), enabling precise decibel-linear gain control via differential voltage inputs (32 dB/V scaling). The attenuator's 100 Ω input resistance is laser-trimmed to ±2%, and its tap points deliver exact 6.02 dB steps.
Gain is calculated as Gain(dB) = 32 × VG + 20 (VG in volts), with VG ranging from −625 mV to +625 mV. Each channel features independent TTL/CMOS-compatible gating (GAT1/GAT2), group delay stability of ±2 ns across gain and frequency, and common-mode rejection up to 30 dB at 100 kHz - all while maintaining flat amplitude response (±0.5 dB) from 100 kHz to 10 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | 0 dB to +40 dB per channel - enables precise time-gain compensation in ultrasound beamforming without digital interpolation. |
| Input Noise Density | 1.4 nV/√Hz - ensures high SNR in low-level signal amplification (e.g., echo reception in medical imaging). |
| −3 dB Bandwidth | 35 MHz - supports wideband RF and video signal conditioning up to 10 MHz with ±0.5 dB flatness. |
| Gain Accuracy | ±0.3 dB absolute - eliminates need for system-level calibration in closed-loop AGC designs. |
| Group Delay Variation | ±2 ns over full gain range and 1–10 MHz - preserves pulse integrity in time-critical applications like sonar and TDR. |
| Supply Voltage | ±4.75 V to ±5.25 V - compatible with standard ±5 V industrial and medical power rails. |
| Output Drive | ±2.5 V into 500 Ω - sufficient to interface directly with 12-bit+ ADCs without external buffering. |
Pinout & Package
AD600JRZ is housed in a 16-lead SOIC package (JEDEC MS-012AC, body width 3.9 mm), rated for 0°C to +70°C operation (J-grade). Thermal resistance θJA is 100°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C1LO / C2LO | CH1/CH2 gain-control low input | Differential input leg; positive voltage reduces gain - used with C1HI/C2HI to set 32 dB/V scaling. |
| C1HI / C2HI | CH1/CH2 gain-control high input | Differential input leg; positive voltage increases gain - together with C1LO/C2LO defines VG = VHI − VLO. |
| A1HI / A2HI | CH1/CH2 signal input high | Inverting input node; accepts differential signals up to ±1.4 V peak with minimal distortion. |
| A1LO / A2LO | CH1/CH2 signal input low | Input ground reference - must connect directly to source ground to preserve gain accuracy and CMRR. |
| GAT1 / GAT2 | CH1/CH2 gating control | TTL/CMOS-compatible logic input; high state blocks signal path and clamps output to within ±10 mV of A1CM/A2CM. |
| A1OP / A2OP | CH1/CH2 output | Single-ended output capable of ±2.5 V into 500 Ω; low 2 Ω output impedance supports driving capacitive loads. |
| A1CM / A2CM | CH1/CH2 output common | Output ground reference - must tie to load ground to maintain common-mode rejection and minimize feedthrough. |
| VPOS / VNEG | Positive/negative supply | Shared dual supplies for both channels; requires local 0.1 µF bypassing at each pin for stability. |
Key Features
| Feature | Design Value |
|---|---|
| X-AMP® architecture | Combines passive R-2R attenuator + fixed-gain amplifier to decouple gain setting from dynamic range handling - enabling low distortion (<−60 dBc THD) even at ±1 V output. |
| Differential gain-control interface | 15 MΩ input resistance and 32 dB/V scaling - allows daisy-chaining multiple AD600JRZ units without loading DAC outputs or requiring level-shifting. |
| Independent signal gating | Sub-μs gating response (0.3 μs) with <±100 mV gated-off offset - essential for zero-latency channel muting in phased-array ultrasound receivers. |
| Stable group delay | ±2 ns variation vs. gain and frequency - preserves phase coherence across channels in multi-element beamforming systems. |
| Laser-trimmed input resistance | 100 Ω ±2% - guarantees accurate gain setting and predictable high-pass corner when used with external series capacitors or termination networks. |
Applications
| Ultrasound Time-Gain Control (TGC) | RF Automatic Gain Control (AGC) |
|---|---|
|
Use Scenario: Amplifying weak acoustic echo signals across depth in diagnostic ultrasound systems, where signal attenuation increases with tissue penetration. IC Role / Device Role / Timing Role: Dual-channel VGA providing synchronized, independently programmable gain per receive channel to compensate for exponential signal loss (≈1 dB/cm/MHz). Use Value: 0 dB to +40 dB linear-in-dB range matches clinical TGC profiles; ±0.3 dB gain accuracy eliminates per-channel calibration; 1.4 nV/√Hz noise floor preserves contrast resolution in deep-tissue imaging. |
Use Scenario: Stabilizing signal amplitude in wideband RF receivers subject to fading, multipath, or antenna coupling variations. IC Role / Device Role / Timing Role: Front-end VGA in IF or baseband chain, dynamically adjusting gain based on RSSI or detector output to maintain constant ADC input level. Use Value: 35 MHz bandwidth supports LTE/WiFi IF frequencies; differential gain control enables seamless integration with DAC-based loop controllers; low THD prevents intermodulation in crowded spectrum environments. |
| High-Speed Data Acquisition Front-End | Precision Signal Measurement System |
|
Use Scenario: Conditioning analog sensor outputs (e.g., piezoelectric, photodiode) prior to digitization in oscilloscopes or transient recorders. IC Role / Device Role / Timing Role: Programmable preamplifier stage with calibrated gain stepping, enabling auto-ranging without relay switching or FPGA-controlled gain selection. Use Value: ±2.5 V output swing into 500 Ω directly interfaces with 12–14 bit ADCs; flat 100 kHz–10 MHz response ensures fidelity across measurement bandwidth; low group delay variation avoids timing skew between channels. |
Use Scenario: Building RMS-to-dB converters or wide-dynamic-range voltmeters requiring >70 dB measurement range and sub-decibel linearity. IC Role / Device Role / Timing Role: Core gain element in feedback-controlled AGC loops with logarithmic detectors, delivering stable, temperature-invariant dB-linear transfer function. Use Value: 32 dB/V gain scaling simplifies DAC-to-gain mapping (e.g., 10 mV/bit = 0.32 dB/bit); ±2 ns group delay stability ensures accurate phase-sensitive measurements; low noise enables detection of µV-level signals in noisy industrial environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar variable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD602JRZ | Same X-AMP® architecture but −10 dB to +30 dB gain range and 31.07 dB fixed amplifier gain; identical 1.4 nV/√Hz noise and 35 MHz bandwidth. | Better output SNR (86 dB vs. 76 dB in 1 MHz BW) due to lower gain, making it preferred for low-distortion, high-SNR receiver chains where maximum gain is not required. | Select AD602JRZ when system dynamic range prioritizes SNR over maximum gain; AD600JRZ remains optimal for deep-TGC or wide-range AGC where 40 dB span is mandatory. |
| LMH6502MA/NOPB | Single-channel, 20 dB to 50 dB gain range; higher 3.5 nV/√Hz input noise; 750 MHz bandwidth; uses current-feedback architecture instead of X-AMP®. | Designed for broadband RF/IF gain control (e.g., cable TV, radar), not precision low-noise analog conditioning; lacks independent gating and differential gain control. | Choose LMH6502MA/NOPB only for ultra-wideband (>100 MHz) applications where speed outweighs noise and gain-linearity requirements; AD600JRZ is superior for medical, test, and measurement use cases demanding accuracy and low noise. |
Compared with AD602JRZ and LMH6502MA/NOPB, the AD600JRZ uniquely balances 40 dB linear-in-dB gain range, 1.4 nV/√Hz noise, ±0.3 dB accuracy, and dual-channel gating - making it irreplaceable in time-critical, multi-channel analog signal conditioning where gain fidelity and channel synchronization are non-negotiable.
Availability
AD600JRZ is available at Aetrix Electronics and suitable for ultrasound imaging systems, RF automatic gain control circuits, and high-speed data acquisition front-ends requiring stable component supply, long-term obsolescence management, and traceable sourcing.
Supply support for AD600JRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design and manufacturing expertise spanning precision instrumentation, industrial automation, and medical electronics.
The AD600JRZ belongs to Analog Devices' X-AMP® family of variable gain amplifiers, engineered specifically for applications demanding linear-in-dB gain control, ultra-low noise, and deterministic group delay - notably ultrasound beamforming, RF receiver AGC, and precision test equipment.
FAQ
What is the operating temperature range for the AD600JRZ?
The AD600JRZ is a J-grade device specified for operation from 0°C to +70°C ambient temperature. It is packaged in a 16-lead SOIC and complies with JEDEC MS-012AC mechanical dimensions. This grade is intended for commercial and industrial applications where extended temperature operation is not required; for −40°C to +85°C, the AD600ARZ (A-grade) should be selected. The AD600JRZ datasheet confirms thermal resistance θJA = 100°C/W under standard PCB conditions.
Does the AD600JRZ support true differential input signals?
No, the AD600JRZ does not accept fully differential input signals. Its signal inputs (A1HI/A1LO and A2HI/A2LO) are pseudo-differential: A1HI and A2HI are inverting inputs referenced to their respective low-side terminals (A1LO, A2LO), which serve as dedicated input ground nodes. These LO pins must connect directly to the source ground to preserve gain accuracy and common-mode rejection. The architecture intentionally separates input and output grounds (via A1CM/A2CM) to manage ground differentials in multi-channel systems - a design choice confirmed in the AD600JRZ functional block diagram and pin descriptions.
What is the maximum output voltage swing for the AD600JRZ into a 100 Ω load?
The AD600JRZ delivers ±1 V peak output into a 100 Ω load, as specified in the "Output Characteristics" section of the datasheet. This is lower than its ±2.5 V capability into 500 Ω due to increased current demand and associated distortion. Driving 100 Ω loads requires careful attention to layout and bypassing; the datasheet notes that THD remains ≤−60 dBc at ±1 V output with 200 Ω || 5 pF load. For higher output drive, an external buffer stage is recommended - the AD600JRZ itself is not designed to sustain full swing into impedances below 200 Ω without performance degradation.
Can the AD600JRZ be used in a cascaded configuration to achieve 80 dB total gain?
Yes, the AD600JRZ supports cascaded operation: connecting A1OP/A1CM to A2HI/A2LO (via AC-coupling capacitor) achieves a nominal −2 dB to +82 dB overall gain range. This configuration is explicitly detailed in the "Achieving 80 dB Gain Range" section of the AD600JRZ datasheet. Two implementation modes are supported - sequential (maximizes SNR) and parallel (minimizes gain error) - with distinct gain-control wiring schemes. The internal 100 Ω input resistance and 500 Ω output impedance ensure predictable interface behavior when cascading, and no external level-shifting is required.
Is the AD600JRZ pin-compatible with the AD602JRZ?
Yes, the AD600JRZ and AD602JRZ share identical pinout, package (16-lead SOIC), and electrical interface - including gain-control, gating, supply, and I/O pin assignments. Both devices use the same X-AMP® architecture and differ only in laser-trimmed fixed-gain amplifier values (41.07 dB vs. 31.07 dB) and resulting gain ranges (0–40 dB vs. −10–+30 dB). This pin compatibility is confirmed in the AD600/AD602 Rev. F datasheet's "Ordering Guide" and "Pin Configuration" sections, enabling drop-in replacement where gain range and SNR requirements align.
AD600JRZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- X-AMP®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Variable Gain
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 275V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 35 MHz
- Current - Input Bias:
- 350 nA
- Voltage - Input Offset:
- -
- Current - Supply:
- 11mA (x2 Channels)
- Current - Output / Channel:
- 50 mA
- Voltage - Supply Span (Min):
- 9.5 V
- Voltage - Supply Span (Max):
- 10.5 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
AD600JRZ FAQ
1.How can I place an order for AD600JRZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD600JRZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD600JRZ reliable?
The price and inventory of AD600JRZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD600JRZ is usually 5 days.
3.What payment methods are accepted for AD600JRZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD600JRZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD600JRZ?
AD600JRZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD600JRZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD600JRZ?
For technical support, including AD600JRZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD600JRZ requirements.
6.How does Aetrix verify that AD600JRZ is sourced from the original manufacturer or authorized distributors?
All AD600JRZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD600JRZ meets industry standards.
7.What is the process for return or replacement of AD600JRZ?
All AD600JRZ units undergo pre-shipment inspection (PSI). If there is an issue with AD600JRZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD600JRZ part is unused and in its original packaging.
Return procedure for AD600JRZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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