My Inquiry
My Account
Analog Devices Inc. AD602ARZ
- Part No.:
- AD602ARZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AD602ARZ.pdf
- Description:
- IC VARIABLE GAIN 2 CIRC 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:522
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD602ARZ from Analog Devices is a dual-channel, low-noise, wideband variable gain amplifier (VGA) optimized for ultrasound time-gain control and precision AGC systems. It delivers −10 dB to +30 dB linear-in-dB gain per channel, 1.4 nV/√Hz input noise, 35 MHz −3 dB bandwidth, and ±2 ns group delay stability across gain settings - enabling high-fidelity signal conditioning in medical imaging front-ends.
For engineers reviewing the AD602ARZ datasheet, AD602ARZ pinout, AD602ARZ application, or AD602ARZ equivalent, this page provides verified technical context, validated pin functions, confirmed gain-control interface behavior, real-world SNR trade-offs vs. AD600, and two rigorously cross-checked alternative VGAs with documented functional differences.
Technical Context
The AD602ARZ implements Analog Devices' proprietary X-AMP® architecture: a 7-stage laser-trimmed R-2R attenuator (0 dB to −42.14 dB) followed by a fixed-gain amplifier (31.07 dB). This topology decouples gain setting from signal path dynamics, ensuring flat amplitude response (±0.5 dB from 100 kHz–10 MHz) and distortion of −60 dBc at ±1 V output into 200 Ω.
Its fully differential gain-control interface offers 32 dB/V scaling (±0.3 dB accuracy), 15 MΩ input resistance, and <1 μs response; each channel includes TTL/CMOS-compatible gating (GAT1/GAT2) that sets output dc level within ±10 mV of A1CM/A2CM while reducing noise spectral density to 65 nV/√Hz in gated-off state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | −10 dB to +30 dB per channel - enables precise time-variable gain compensation in ultrasound beamforming without clipping at ±1 V output into 100 Ω. |
| Input Noise Density | 1.4 nV/√Hz - ensures 86 dB SNR (1 MHz BW) at 1 Vrms output, critical for detecting weak echo signals in medical imaging. |
| −3 dB Bandwidth | 35 MHz - supports wideband RF/IF signal processing up to 10 MHz with ±0.5 dB flatness and ±2 ns group delay variation. |
| Gain Accuracy | ±0.3 dB over full range - guarantees repeatable gain calibration in automated test equipment and closed-loop AGC systems. |
| Output Drive | ±1 V into 100 Ω or ±2.5 V into 500 Ω - directly interfaces with 12-bit+ ADCs (e.g., AD9226) without external buffering. |
| Power Dissipation | 125 mW max per amplifier - allows dual-channel operation in thermally constrained portable ultrasound modules. |
| Signal Gating | TTL/CMOS-compatible (0.8 V / 2.4 V thresholds) with 0.3 μs response - enables synchronized channel muting in phased-array receivers. |
Pinout & Package
AD602ARZ is housed in a 16-lead SOIC package (body width 3.9 mm, JEDEC MS-012AC), rated for −40°C to +85°C operation (A-grade).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C1LO / C2LO | CH1/CH2 gain-control low input | Differential reference for 32 dB/V attenuation control; positive voltage reduces gain - used with C1HI/C2HI to set precise dB gain. |
| C1HI / C2HI | CH1/CH2 gain-control high input | Differential active input for gain control; 0 V differential yields 10 dB nominal gain (AD602); requires 15 MΩ source impedance. |
| A1HI / A2HI | CH1/CH2 signal input high | Inverting input node for differential signal pair; accepts ±1.4 V peak with minimal distortion when driven from 50 Ω source. |
| A1LO / A2LO | CH1/CH2 signal input low | Input ground reference - must connect directly to source ground to maintain gain accuracy and CMRR >30 dB at 100 kHz. |
| GAT1 / GAT2 | CH1/CH2 gating control | Active-high logic input (TTL/CMOS) that blocks signal path and forces output to A1CM/A2CM within ±10 mV. |
| A1OP / A2OP | CH1/CH2 output | Single-ended output capable of ±1 V into 100 Ω; dc-coupled and optimized for driving ADC inputs or cascaded amplifiers. |
| A1CM / A2CM | CH1/CH2 output common | Output ground reference - must tie to load ground to preserve output offset (<30 mV) and minimize feedthrough during gating. |
| VPOS / VNEG | Positive/negative supply | ±4.75 V to ±5.25 V dual supply; quiescent current 11–14 mA per channel - supports low-noise biasing with standard LDOs. |
Key Features
| Feature | Design Value |
|---|---|
| X-AMP® architecture | Decouples gain control from signal path via passive R-2R attenuator + fixed-gain amplifier - eliminates gain-dependent distortion and phase shift. |
| Linear-in-dB gain law | 32 dB/V scaling with ±0.3 dB absolute error - enables direct DAC-driven gain programming without lookup tables or calibration. |
| Independent channel gating | Sub-microsecond TTL/CMOS gating with <±100 mV output offset - suppresses crosstalk in multi-channel summing architectures like ultrasound beamformers. |
| Stable group delay | ±2 ns variation vs. gain or frequency (1–10 MHz) - preserves pulse fidelity in time-of-flight measurements and digital beamforming. |
| Laser-trimmed input resistance | 100 Ω ±2% (pins 2–3, 6–7) - ensures accurate gain setting and predictable high-pass corner when used with external series capacitors. |
Applications
| Ultrasound Time-Gain Control (TGC) | High-Performance Audio AGC |
|---|---|
|
Use Scenario: Compensating for acoustic attenuation in soft tissue during B-mode ultrasound scanning, requiring 40–60 dB dynamic gain adjustment over 10–20 μs intervals. IC Role / Device Role / Timing Role: Dual-channel VGA providing synchronized, linear-in-dB gain ramp per scan line - CH1/CH2 independently controlled by FPGA-generated voltage ramps. Use Value: 1.4 nV/√Hz noise floor and 35 MHz bandwidth preserve echo signal integrity from near-field to far-field, enabling sub-millimeter resolution. |
Use Scenario: Maintaining consistent output level in professional audio mixers handling microphone inputs with 100 dB dynamic range. IC Role / Device Role / Timing Role: Precision AGC core where gain is updated every 10–100 ms based on RMS-detected envelope - leveraging AD602ARZ's stable 32 dB/V interface. Use Value: ±0.3 dB gain accuracy and −60 dBc THD ensure transparent level correction without introducing harmonic artifacts or pumping artifacts. |
| Radar IF Signal Conditioning | Automated Test Equipment (ATE) Front-End |
|
Use Scenario: Amplifying downconverted FMCW radar IF signals (1–20 MHz) with adaptive gain to maintain constant ADC input level across varying target distances. IC Role / Device Role / Timing Role: Wideband VGA placed between mixer and 12-bit ADC - gain dynamically adjusted via DAC-controlled C1HI/C1LO to prevent saturation. Use Value: 35 MHz bandwidth and ±2 ns group delay stability preserve chirp linearity for accurate range-Doppler processing. |
Use Scenario: Programmable gain stage in modular ATE systems measuring sensor outputs (e.g., strain gauges, thermocouples) with 80 dB dynamic range requirements. IC Role / Device Role / Timing Role: Dual-channel gain element supporting parallel test of two DUTs - each channel independently calibrated using on-board reference voltages. Use Value: Laser-trimmed 100 Ω input resistance and ±0.3 dB gain error enable traceable, NIST-aligned gain calibration without per-unit firmware compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar variable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD600ARZ | Higher gain range (0 dB to +40 dB), same 1.4 nV/√Hz noise, but 76 dB SNR (vs. AD602ARZ's 86 dB) due to +10 dB higher fixed-gain stage. | Better suited for low-level signal amplification where maximum gain is prioritized over SNR - e.g., seismic sensor preamps. | Select AD600ARZ only when >30 dB gain is required and SNR >80 dB is not critical; AD602ARZ preferred for ultrasound TGC where SNR dominates. |
| VCA82x series (e.g., VCA824IPWPR) | Single-channel, 45 MHz bandwidth, 2.1 nV/√Hz noise, 30 dB/V gain control, no integrated gating - requires external logic for channel muting. | Targeted at broadband communications (CATV, DOCSIS) with emphasis on high-frequency linearity over low-noise precision. | Choose VCA824IPWPR for cost-sensitive, single-channel RF AGC where 35 MHz bandwidth suffices and gating is implemented externally. |
Compared with AD600ARZ, AD602ARZ trades 10 dB max gain for 10 dB better SNR - making it optimal for weak-signal detection; versus VCA824IPWPR, AD602ARZ offers dual channels, lower noise, integrated gating, and tighter gain accuracy at the expense of slightly lower bandwidth and higher unit cost.
Availability
AD602ARZ is available at Aetrix Electronics and suitable for ultrasound imaging systems, high-fidelity audio AGC circuits, radar IF signal chains, and automated test equipment requiring stable component supply, guaranteed A-grade temperature performance, and long-term manufacturing continuity.
Supply support for AD602ARZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technologies, headquartered in Norwood, MA, serving industrial, automotive, communications, and healthcare markets since 1965.
The AD602ARZ belongs to Analog Devices' X-AMP® family of precision variable gain amplifiers, designed specifically for applications demanding linear-in-dB control, ultra-low noise, and wideband fidelity - especially medical ultrasound and test instrumentation.
FAQ
What is the guaranteed operating temperature range for AD602ARZ?
The AD602ARZ is an A-grade device rated for continuous operation from −40°C to +85°C. This specification is validated per Analog Devices' Rev. F datasheet and applies to the 16-lead SOIC package (ARZ suffix). It is not rated for extended military or space-grade environments - those require the S-grade AD602S variant in CERDIP packaging.
Does AD602ARZ support true differential input signaling?
No, AD602ARZ does not implement fully differential input stages. Its A1HI/A1LO and A2HI/A2LO pins provide pseudo-differential interfaces where A1LO and A2LO serve as dedicated input ground references - not complementary signal inputs. True differential operation requires external resistive networks or pairing with a separate differential driver.
How is gain controlled on AD602ARZ, and what voltage range is required?
AD602ARZ uses a fully differential gain-control interface (C1HI/C1LO and C2HI/C2LO) with 32 dB/V scaling. A differential voltage of −625 mV yields −10 dB gain; +625 mV yields +30 dB gain. The interface draws <1 μA and presents 15 MΩ input resistance - compatible with standard DAC outputs when referenced to the respective LO pin.
Can AD602ARZ drive a 50 Ω load directly?
AD602ARZ is not specified to drive 50 Ω loads continuously. Its output is characterized for 100 Ω (±1 V) and 500 Ω (±2.5 V). Driving 50 Ω may cause excessive power dissipation, thermal stress, and degraded THD (−60 dBc spec assumes ≥100 Ω). For 50 Ω systems, use an external buffer amplifier such as the ADA4897-1.
What is the purpose of the A1CM and A2CM pins on AD602ARZ?
A1CM and A2CM are output common (ground) reference pins for Channel 1 and Channel 2, respectively. They must be connected to the load ground to maintain output offset accuracy (<30 mV) and minimize gating feedthrough. Unlike A1LO/A2LO (input grounds), A1CM/A2CM define the dc reference for the output stage - critical for proper gating function and common-mode rejection.
AD602ARZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- X-AMP®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Variable Gain
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 275V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 35 MHz
- Current - Input Bias:
- 350 nA
- Voltage - Input Offset:
- -
- Current - Supply:
- 11mA (x2 Channels)
- Current - Output / Channel:
- 50 mA
- Voltage - Supply Span (Min):
- 9.5 V
- Voltage - Supply Span (Max):
- 10.5 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
AD602ARZ FAQ
1.How can I place an order for AD602ARZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD602ARZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD602ARZ reliable?
The price and inventory of AD602ARZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD602ARZ is usually 5 days.
3.What payment methods are accepted for AD602ARZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD602ARZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD602ARZ?
AD602ARZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD602ARZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD602ARZ?
For technical support, including AD602ARZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD602ARZ requirements.
6.How does Aetrix verify that AD602ARZ is sourced from the original manufacturer or authorized distributors?
All AD602ARZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD602ARZ meets industry standards.
7.What is the process for return or replacement of AD602ARZ?
All AD602ARZ units undergo pre-shipment inspection (PSI). If there is an issue with AD602ARZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD602ARZ part is unused and in its original packaging.
Return procedure for AD602ARZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD602ARZ Tags
-
LM358DT
STMicroelectronics
-
LM358DR
Texas Instruments
-
LM2904DR
Texas Instruments
-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments
-
MCP6006T-E/OT
Microchip Technology
-
MCP6006UT-E/OT
Microchip Technology
-
LM324PWR
Texas Instruments
-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments
-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
