Analog Devices Inc. AD606JNZ

Overview

AD606JNZ from Analog Devices is a monolithic 50 MHz demodulating logarithmic amplifier with integrated limiter output, delivering 80 dB dynamic range (–75 dBm to +5 dBm), 37.5 mV/dB logarithmic slope at 10.7 MHz, ±3° phase stability over 80 dB input range at 10.7 MHz, and single +5 V supply operation. It serves as an RSSI core in IF signal chains for ultrasound, sonar, and RF receivers.

For engineers reviewing the AD606JNZ datasheet, AD606JNZ pinout, AD606JNZ application, or AD606JNZ equivalent, this page delivers verified specifications, functional pin mapping, real-world use cases in RF measurement and limiting amplification, and validated alternative options for receiver front-end design.

Technical Context

The AD606JNZ implements a 9-stage successive-detection architecture with differential RF inputs (INHI/INLO), on-chip offset-nulling loop using FIL1/FIL2 filter nodes, and dual-output capability: buffered voltage-mode logarithmic output (VLOG) and open-collector current-mode limiter outputs (LMHI/LMLO). Its logarithmic transfer function follows VLOG = 0.5 V at –75 dBm and 3.5 V at +5 dBm, with conformance within ±0.4 dB over that range.

It integrates two independent low-pass filtering paths: a three-pole post-demodulation filter driving VLOG (2 MHz corner, 150 ns rise time), and an offset-nulling loop with user-adjustable cutoff via external capacitor CZ. The limiter path delivers 1.2 mA full-scale differential current with <1.5 ns transition time and hard-limiting behavior up to 100 MHz.

Key Specifications

Pinout & Package

AD606JNZ is packaged in a 16-lead plastic DIP (N-16 package), through-hole mountable, with 0.3" wide body and standard 0.1" pin pitch. Pin 1 is located at the left end of the top row when viewed from top with notch or dot oriented upward.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar logarithmic amplifier applications.

Compared with AD8307ARZ and LT5537IMS8#TRPBF, the AD606JNZ uniquely combines 80 dB logarithmic accuracy with a fully differential, current-mode limiter output in a single 16-pin DIP-enabling direct integration into legacy IF architectures without redesigning signal routing or power domains.

Availability

AD606JNZ is available at Aetrix Electronics and suitable for ultrasound beamforming, RF spectrum analysis, and GSM receiver design requiring stable component supply, long-term obsolescence management, and traceable commercial-temperature DIP sourcing.

Supply support for AD606JNZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA, with design centers worldwide.

The AD606JNZ belongs to Analog Devices' precision RF logarithmic amplifier product line, engineered specifically for high-dynamic-range, phase-stable IF signal processing in test equipment, medical imaging, and wireless communications infrastructure.

FAQ

What is the maximum input frequency supported by the AD606JNZ in logarithmic mode?

The AD606JNZ supports logarithmic amplification up to 50 MHz under AC-coupled sinusoidal input conditions. Its specified log amp f_MAX is 50 MHz at ±0.4 dB conformance over –75 dBm to +5 dBm. Performance degrades above this frequency due to detector stage bandwidth limits, though usable log response extends beyond 50 MHz with reduced accuracy. The AD606JNZ limiter path operates to 100 MHz independently.

How does the AD606JNZ achieve phase stability across its 80 dB input range?

The AD606JNZ achieves ±3° phase stability from –75 dBm to +5 dBm at 10.7 MHz through matched 9-stage limiting amplifier design, precision biasing that stabilizes gain per stage at 11.15 dB, and symmetric differential signal path layout. This stability is measured at the limiter outputs (LMHI/LMLO) and is essential for coherent demodulation. The AD606JNZ maintains this spec only when both inputs (INHI/INLO) are driven differentially with matched source impedance.

Can the AD606JNZ operate from a supply voltage other than +5 V?

Yes, the AD606JNZ operates from +4.5 V to +5.5 V. Its logarithmic slope scales linearly with supply voltage (V_Y = 0.15 × V_POS), so 37.5 mV/dB at +5 V becomes 33.75 mV/dB at +4.5 V and 41.25 mV/dB at +5.5 V. Intercept remains supply-independent. For stable scaling in ADC-based systems, V_POS should be regulated to ±1% to hold slope error within ±1%. The AD606JNZ powered-up current varies from 13 mA to 20 mA across temperature and supply.

What is the purpose of the FIL1 and FIL2 pins on the AD606JNZ?

FIL1 and FIL2 are terminals of the internal offset-nulling low-pass filter (15 kHz corner). Connecting an external capacitor C_Z between them lowers the filter cutoff frequency-enabling stable log operation down to ~25 Hz with proper C_Z/C_C ratio. Without external capacitance, the AD606JNZ is optimized for >10 MHz IF applications. FIL1 and FIL2 must remain unconnected unless sub-MHz operation is required; incorrect C_Z values cause ringing and log distortion during pulsed RF or power-up transitions.

Is the AD606JNZ pin-compatible with other members of the AD606 family?

Yes, the AD606JNZ (16-lead plastic DIP) shares identical pinout and electrical characteristics with AD606JR (SOIC) and AD606JCHIPS (die). All variants specify 0°C to +70°C operation and match in dynamic range, slope, phase stability, and power-down behavior. Mechanical differences exist only in package type and thermal resistance (θ_JA = 85°C/W for DIP vs. 100°C/W for SOIC), but no circuit redesign is needed when substituting AD606JNZ for AD606JR in existing layouts.