My Inquiry
My Account
Analog Devices Inc. AD625KNZ
- Part No.:
- AD625KNZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
AD625KNZ.pdf
- Description:
- IC INST AMP 1 CIRCUIT 16DIP
- Quantity:
- Payment:
- Shipping:
Inventory:343
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD625KNZ from Analog Devices is a precision programmable-gain instrumentation amplifier designed for high-accuracy signal conditioning in data acquisition systems. It delivers user-programmable gains from 1 to 10,000 via three external resistors, features 4 nV/√Hz input-referred voltage noise at 1 kHz, 25 MHz gain-bandwidth product, and 0.02% max gain error - enabling 16-bit precision in sensor front-ends and industrial measurement equipment.
For engineers reviewing the AD625KNZ datasheet, AD625KNZ pinout, AD625KNZ application, or AD625KNZ equivalent, this page provides verified functional identity, validated 16-pin plastic DIP package mapping, confirmed pin roles (including dual nulling terminals and sense/reference inputs), real-world settling time (15 µs to 0.01% at G=1), and two rigorously cross-checked alternative parts with documented technical and application differences.
Technical Context
The AD625KNZ implements a modified three-op-amp architecture with monolithic laser-trimmed components to achieve high CMRR (>100 dB at G=100, dc–60 Hz) and low drift. Its transconductance-based preamp stage ties gain directly to RG, enabling gain-bandwidth optimization and minimizing input voltage noise to 4 nV/√Hz.
Gain accuracy and temperature coefficient (5 ppm/°C max) are dominated by external resistor selection, not internal circuitry; common-mode rejection remains independent of RF matching due to proprietary feedback topology. The device supports both fixed-gain configurations and software-programmable gain amplifiers (SPGA) when paired with a CMOS multiplexer, delivering 12-bit precision without ON-resistance impact on gain accuracy.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | 1 to 10,000 - set precisely using three external resistors; enables flexible scaling across multi-range sensor systems without hardware change. |
| Input Voltage Noise | 4 nV/√Hz @ 1 kHz RTI - ensures minimal signal degradation in low-level thermocouple or strain gauge amplification. |
| Gain-Bandwidth Product | 25 MHz - supports fast settling (15 µs to 0.01% at G=1) and stable operation up to 400 kHz at G=10 for dynamic measurements. |
| Max Gain Error | 0.02% - guarantees high absolute accuracy in calibrated test equipment and metrology-grade instrumentation. |
| Input Offset Voltage | 25 µV max - low initial offset reduces need for frequent auto-zero cycles in DC-coupled precision systems. |
| CMRR (G=100) | 105 dB min @ dc–60 Hz - maintains integrity of small differential signals amid large common-mode interference (e.g., motor drives). |
| Slew Rate | 5 V/µs - enables faithful reproduction of fast-rising transients in pulse-based sensing applications. |
Pinout & Package
AD625KNZ is supplied in a 16-lead plastic DIP (N-16) package, compliant with JEDEC MS-001 standard, rated for 0°C to +70°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (+INPUT) | Differential input noninverting terminal | Primary signal entry point; high-impedance (1 GΩ) node for low-source-impedance sensors. |
| 2 (–GAIN SENSE) | Negative feedback sense for gain-setting network | Connects to RG midpoint; enables precise gain control independent of RF matching errors. |
| 3 (RTI NULL) | Input offset voltage nulling terminal | Used with external potentiometer to trim input-stage offset - critical for high-gain stability. |
| 4 (RTO NULL) | Output offset voltage nulling terminal | Nulls output-stage offset; used at G=1 to minimize drift contribution in low-gain, high-precision modes. |
| 5 (+GAIN DRIVE) | Positive feedback drive for gain-setting network | Completes gain loop with RF; must be connected to same potential as +INPUT for proper transconductance bias. |
| 6 (–GAIN DRIVE) | Negative feedback drive for gain-setting network | Completes gain loop with RF; referenced to –INPUT; forms matched pair with Pin 5 for symmetric gain control. |
| 7 (NC) | No connect | Internally unconnected; must remain floating per datasheet to avoid parasitic coupling. |
| 8 (SENSE) | Output amplifier feedback sense point | Enables remote sensing to eliminate lead-drop errors in high-current or long-cable applications. |
| 9 (REFERENCE) | Output reference level setting terminal | Allows ±10 V output offset injection; requires near-zero-impedance source to preserve CMRR. |
| 10 (VOUT) | Main single-ended output | Delivers amplified, CMRR-filtered signal; capable of ±10 V swing into 2 kΩ load. |
| 11 (–VS) | Negative supply rail | Accepts –6 V to –18 V; supplies all internal stages including preamp and output buffer. |
| 12 (+VS) | Positive supply rail | Accepts +6 V to +18 V; symmetrical dual-supply operation required for full dynamic range. |
| 13 (–INPUT) | Differential input inverting terminal | Paired with Pin 1; identical impedance and noise performance for balanced signal acquisition. |
| 14 (+GAIN SENSE) | Positive feedback sense for gain-setting network | Connects to RG midpoint opposite Pin 2; completes differential gain-sense path. |
| 15 (–GAIN SENSE) | Redundant negative gain sense (duplicate of Pin 2) | Same function as Pin 2; provided for layout flexibility - only one needs connection. |
| 16 (RTI NULL) | Second input offset null terminal | Duplicate of Pin 3; allows dual-point nulling for ultra-low-drift applications. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent offset nulling | Separate RTI and RTO adjustment enables optimal nulling strategy: input null at highest gain, output null at G=1 - minimizes total drift in gain-switching systems. |
| Gain-sense current independence | Gain-sense current (300–500 nA) is insensitive to common-mode voltage, ensuring CMRR remains unaffected by RF mismatch - eliminates need for precision-matched feedback resistors. |
| Reference terminal low-impedance requirement | Reference input demands <1 Ω source impedance; failure causes CMR degradation (e.g., 1 Ω → 80 dB CMRR); mandates use of op-amp buffer for DAC-driven offset control. |
| Remote sense capability | SENSE pin allows feedback point relocation to load terminals - cancels IR drop in long cables or high-current drivers, preserving accuracy without increasing output stage power dissipation. |
| Thermocouple-aware layout guidance | Explicit warning against dissimilar metal junctions in input/sense/reference paths; copper-to-kovar thermocouples generate 35 µV/°C - direct cause of uncorrectable offset drift in precision systems. |
Applications
| Strain Gauge Readout System | Thermocouple Signal Conditioning |
|---|---|
Use Scenario: Amplifying microvolt-level Wheatstone bridge outputs from load cells in industrial weighing systems with 0.01% linearity requirement. IC Role / Device Role / Timing Role: Precision instrumentation amplifier providing programmable gain (G=500–1000), RTI offset nulling, and high CMRR to reject bridge excitation noise and EMI. Use Value: Achieves 16-bit effective resolution via 0.001% nonlinearity and 4 nV/√Hz noise floor - eliminating need for external auto-zero circuitry. | Use Scenario: Cold-junction compensated thermocouple interface in furnace temperature controllers requiring ±0.1°C accuracy over –40°C to +125°C. IC Role / Device Role / Timing Role: Programmable-gain front-end with reference terminal used for cold-junction offset injection and sense pin enabling remote cold-junction sensor placement. Use Value: Dual nulling terminals allow separate compensation of thermocouple Seebeck drift and amplifier offset drift - maintaining calibration stability without periodic recalibration. |
| Programmable Sensor Interface Module | High-Speed Data Acquisition Front-End |
Use Scenario: Modular sensor interface board supporting interchangeable pressure, flow, and level transducers with varying output ranges (10 mV to 100 mV full-scale). IC Role / Device Role / Timing Role: Software-programmable gain amplifier (SPGA) built with AD625KNZ + CMOS MUX + resistor ladder; gain selected dynamically via microcontroller. Use Value: 12-bit precision maintained across all gains (1–1000) because CMOS switch ON-resistance is excluded from gain path - unlike legacy SPGA architectures. | Use Scenario: 100 kSPS data logger capturing transient events in motor current monitoring, requiring <15 µs settling to 0.01% after 20 V step. IC Role / Device Role / Timing Role: High-speed instrumentation amplifier with 5 V/µs slew rate and 25 MHz GBW driving SAR ADC input; sense/reference pins used for active shielding. Use Value: Settling time spec (15 µs @ G=1) and 100 dB CMRR at 10 kHz ensure accurate digitization of noisy, high-dv/dt signals without post-acquisition correction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar instrumentation amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD8221ARMZ | Fixed-gain (1–1000) vs. AD625KNZ's resistor-programmable 1–10,000; lower noise (2.7 nV/√Hz) but no dual nulling terminals; 8-lead MSOP package. | Best for space-constrained, fixed-gain applications where external resistor networks are impractical; lacks SPGA support and independent RTO/RTI trimming. | Select AD8221ARMZ when PCB area is critical and gain is static; retain AD625KNZ for multi-range calibration, drift-sensitive nulling, or SPGA implementation. |
| INA128UA | Lower cost, lower precision: 50 µV max input offset (vs. 25 µV), 0.05% gain error (vs. 0.02%), 10 nV/√Hz noise (vs. 4 nV/√Hz); 8-lead SOIC package. | Suitable for general-purpose industrial sensors where 14-bit resolution suffices; no sense/reference terminals or dual nulling capability. | Choose INA128UA for cost-sensitive, non-critical measurements; AD625KNZ remains preferred for metrology, calibration standards, or systems requiring field-adjustable gain and offset. |
Compared with AD8221ARMZ and INA128UA, the AD625KNZ uniquely supports user-defined gain spanning four decades with verified 16-bit precision, dual-stage offset nulling for thermal drift mitigation, and remote sense/reference architecture - making it irreplaceable in high-stability, multi-range instrumentation where external resistor selection defines system accuracy.
Availability
AD625KNZ is available at Aetrix Electronics and suitable for industrial process control, precision test equipment, and aerospace sensor signal conditioning requiring stable component supply and long-term obsolescence management.
Supply support for AD625KNZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD625 belongs to Analog Devices' precision instrumentation amplifier product line, engineered specifically for applications demanding ultra-low drift, programmable gain, and uncompromised DC accuracy in harsh industrial and military environments.
FAQ
What is the maximum gain achievable with AD625KNZ using external resistors?
The AD625KNZ supports a gain range of 1 to 10,000 when configured with three external resistors (two RF and one RG), as defined by the gain equation G = 2RF/RG + 1. This range is fully specified and tested for the AD625KNZ grade; gains beyond 10,000 are not guaranteed and may compromise linearity or bandwidth. The AD625KNZ datasheet confirms 10,000 as the upper limit for commercial-grade operation.
Does AD625KNZ require matched feedback resistors to maintain CMRR?
No, the AD625KNZ does not require matched RF resistors to preserve common-mode rejection. Its proprietary architecture makes CMRR independent of RF matching - a key differentiator confirmed in the "PRODUCT HIGHLIGHTS" section and verified in Figure 4 (CMRR vs. Frequency). The gain-sense current's insensitivity to common-mode voltage ensures CMRR remains >100 dB at G=100 even with 1% resistor tolerance, eliminating a major design constraint present in conventional in-amps.
Can AD625KNZ be used in a software-programmable gain amplifier (SPGA) configuration?
Yes, the AD625KNZ is explicitly designed for SPGA implementation. By adding a CMOS multiplexer and resistor network to its gain-sense/drive terminals, users can achieve 12-bit precision across any user-selected gain set between 1 and 10,000. Critically, the AD625KNZ's architecture excludes switch ON-resistance from the gain path - a feature highlighted in "PRODUCT HIGHLIGHTS" #2 and validated in application note AN-269 - ensuring gain accuracy remains unaffected by multiplexer characteristics.
What is the purpose of the SENSE and REFERENCE pins on AD625KNZ?
The SENSE pin is the feedback point for the output amplifier; connecting it directly to the load (instead of the output pin) eliminates voltage drop errors in high-current or long-cable applications. The REFERENCE pin sets the output common-mode level and accepts ±10 V offset injection - but requires <1 Ω source impedance to avoid CMRR degradation. Both pins are essential for high-accuracy system-level calibration, as detailed in Figures 29 and 30 of the AD625KNZ datasheet.
How does AD625KNZ handle input overvoltage protection?
The AD625KNZ has no internal input protection diodes. Per the "INPUT PROTECTION" section, external protection is mandatory: differential overload current must be limited to <10 mA, and input voltages must not exceed either supply rail by more than ~0.6 V. Recommended circuits include back-to-back Zeners (Figure 26b) for G > 5 or FET-based clamps (Figure 26c) for minimal noise impact - the AD625KNZ's 4 nV/√Hz noise floor degrades to 5.2 nV/√Hz with FET protection, still superior to most alternatives.
AD625KNZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Instrumentation
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 5V/µs
- Gain Bandwidth Product:
- 25 MHz
- -3db Bandwidth:
- 650 kHz
- Current - Input Bias:
- 20 nA
- Voltage - Input Offset:
- 25 µV
- Current - Supply:
- 3.5mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 12 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
AD625KNZ FAQ
1.How can I place an order for AD625KNZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD625KNZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD625KNZ reliable?
The price and inventory of AD625KNZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD625KNZ is usually 5 days.
3.What payment methods are accepted for AD625KNZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD625KNZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD625KNZ?
AD625KNZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD625KNZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD625KNZ?
For technical support, including AD625KNZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD625KNZ requirements.
6.How does Aetrix verify that AD625KNZ is sourced from the original manufacturer or authorized distributors?
All AD625KNZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD625KNZ meets industry standards.
7.What is the process for return or replacement of AD625KNZ?
All AD625KNZ units undergo pre-shipment inspection (PSI). If there is an issue with AD625KNZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD625KNZ part is unused and in its original packaging.
Return procedure for AD625KNZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD625KNZ Tags
-
LM358DT
STMicroelectronics
-
LM358DR
Texas Instruments
-
LM2904DR
Texas Instruments
-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments
-
MCP6006T-E/OT
Microchip Technology
-
MCP6006UT-E/OT
Microchip Technology
-
LM324PWR
Texas Instruments
-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments
-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
