My Inquiry
My Account
Analog Devices Inc. AD640JNZ
- Part No.:
- AD640JNZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
AD640JNZ.pdf
- Description:
- IC LOGARITHMIC 1 CIRCUIT 20DIP
- Quantity:
- Payment:
- Shipping:
Inventory:1,447
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD640JNZ from Analog Devices is a fully calibrated, monolithic DC-coupled logarithmic amplifier optimized for precision RF/IF signal compression from DC to 120 MHz. It delivers 50 dB dynamic range with ±1 dB absolute accuracy (dc–100 mV), 1 mA/decade logarithmic output current, and stable 10 dB/stage × 5-stage cascaded architecture. It serves as the core demodulating detector in radar IF receivers requiring traceable amplitude measurement.
For engineers reviewing the AD640JNZ datasheet, AD640JNZ pinout, AD640JNZ application, or AD640JNZ equivalent, this page provides verified technical context, military-grade temperature stability data, real-world AC linearity performance at 30–120 MHz, and validated alternatives for wide-dynamic-range logarithmic detection systems.
Technical Context
The AD640JNZ implements five dc-coupled, fully differential amplifier/limiter stages-each with 10 dB small-signal gain and 350 MHz –3 dB bandwidth-feeding dedicated full-wave transconductance detectors. Its logarithmic transfer function IOUT = IY log|VIN/VX| is laser-trimmed for ±1 dB absolute accuracy over 0°C to +70°C, with VX = 0.99 mV (typ) and IY = 1.00 mA (typ).
It integrates on-chip slope and intercept bias regulators, an X10 attenuator (20 dB, pins 2–5), dual polarity current outputs (LOG OUT/Pin 14, LOG COM/Pin 13), and balanced signal outputs (SIG+OUT/Pin 10, SIG–OUT/Pin 11) at +50 dB gain. Input impedance is 500 kΩ || 2 pF; thermal recovery tails are minimized via low-power PTAT-biased transistor design.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Dynamic Range | 50 dB (dc to 120 MHz), verified for ±0.75 mV to ±200 mV dc inputs with ±1 dB total absolute accuracy |
| Logarithmic Slope | 1.00 mA/decade (±2% over 0°C–70°C), enabling direct 1 V/decade voltage conversion using internal 1 kΩ resistors |
| Intercept Voltage | 0.99 mV (typ), calibrated to ±0.10 mV over temperature-defines 0 dB point of log response at dc/square wave |
| Bandwidth | 145 MHz (full 5-stage path, pins 1/20 → 10/11), with 350 MHz per stage-supports baseband pulse fidelity up to 120 MHz |
| Supply Range | ±4.5 V to ±7.5 V (±6.5 V typical), consuming 9 mA (+VS) / 35 mA (–VS) at TA = +25°C for 220 mW operation |
| Input Offset | 50 µV (typ), <300 µV over full commercial temp range-ensures sub-mV dc measurement integrity |
| Noise Floor | 2 nV/√Hz (1 kHz–10 MHz), yielding –80 dBm noise floor at 100 MHz BW-critical for low-level RF detection |
Pinout & Package
AD640JNZ is supplied in a 20-lead plastic DIP (N-package) with 0.300″ wide body, 0.100″ lead pitch, and standard through-hole mounting. Pin 1 identifier is a notch or beveled corner; pin numbering is counterclockwise from top-left when viewed from top.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 20 | SIG+IN / SIG–IN | Differential signal input pair; 500 kΩ || 2 pF impedance, ±300 mV max common-mode range |
| 2, 3, 4, 5, 19 | ATN IN / ATN LO / ATN COM ×2 | On-chip 20 dB attenuator network; enables ±7.5 mV to ±2 V input range with temperature-stabilized intercept |
| 7, 12 | –VS / +VS | Split analog supplies; ±4.5 V to ±7.5 V operation; quiescent currents 35 mA / 9 mA respectively |
| 8 | ITC | Internal temperature compensation enable; grounding disables ITC bias for attenuator-mode operation |
| 10, 11 | SIG+OUT / SIG–OUT | +50 dB balanced signal output; ±180 mV peak differential, 75 Ω output impedance-supports cascade staging |
| 13, 14 | LOG COM / LOG OUT | Dual-polarity logarithmic current outputs; 1 mA/decade slope, complementary scaling (±1 mA/decade) |
| 15, 16, 17 | RG2 / RG1 / RG0 | Access points for internal 1 kΩ slope-setting resistors; configurable for 0.5 V/dec, 1 V/dec, or 2 V/dec voltage output |
| 6, 9, 18 | BL1 / BL2 / COM | Bias loop terminals and circuit common; BL1/BL2 stabilize gain/slope regulators; COM is signal reference ground |
Key Features
| Feature | Design Value |
|---|---|
| Fully calibrated monolithic system | Laser-trimmed slope (IY) and intercept (VX) guarantee ±1 dB absolute accuracy without external calibration |
| Dual polarity logarithmic outputs | LOG OUT (Pin 14) and LOG COM (Pin 13) provide complementary 1 mA/decade and –1 mA/decade currents for differential readout |
| DC-coupled differential signal path | Eliminates interstage coupling capacitors; enables subsonic (<20 Hz) and true dc amplitude measurement |
| On-chip 20 dB attenuator | Extends input range to ±2 V while stabilizing intercept over temperature via +0.30%/°C TC trimming |
| Thermal recovery optimization | Minimized "tails" after large-signal events-enables accurate detection of small signals immediately following high-level pulses |
| Cascade-ready signal outputs | +50 dB balanced outputs (Pins 10/11) allow direct connection of second AD640JNZ for 95 dB dynamic range extension |
Applications
| Radar IF Signal Compression | Ultrasonic Time-of-Flight Measurement |
|---|---|
|
Use Scenario: Detecting echo amplitudes across 80 dB range in pulsed Doppler radar receivers operating at L/S-band. IC Role / Device Role / Timing Role: Primary logarithmic detector converting RF envelope to baseband current proportional to log(VIN); replaces discrete hybrid IF strips. Use Value: Delivers ±1 dB amplitude accuracy from –75 dBm to +5 dBm inputs at 120 MHz, enabling precise target RCS estimation without recalibration. |
Use Scenario: Measuring transit time of ultrasonic pulses in industrial flow meters with variable fluid attenuation (20–100 dB range). IC Role / Device Role / Timing Role: DC-coupled logarithmic front-end conditioning echo amplitude prior to zero-crossing timing circuits. Use Value: Maintains sub-µs timing jitter by eliminating coupling capacitor drift; 500 kΩ input impedance prevents transducer loading. |
| Precision RF Power Metering | Audio Dynamic Range Compression |
|
Use Scenario: Calibrated RF power measurement in lab-grade spectrum analyzers covering 100 kHz–120 MHz. IC Role / Device Role / Timing Role: Absolute amplitude reference stage providing traceable dBm output via 1 mA/decade current scaled to 1 V/decade. Use Value: Achieves ±0.55 dB total DC linearity error (±1 mV to ±100 mV), meeting MIL-STD-45662A calibration requirements. |
Use Scenario: Real-time dynamic range reduction in professional audio mixers handling 100 dB vocal/instrument peaks. IC Role / Device Role / Timing Role: Wideband logarithmic compressor feeding op-amp integrator for VCA control voltage generation. Use Value: 145 MHz bandwidth preserves transient fidelity; 2 nV/√Hz noise ensures >90 dB SNR in 20 Hz–20 kHz band. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar logarithmic amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD8307ARZ | Single-supply (2.7–5.5 V), 500 MHz bandwidth, 1 V/decade output voltage (not current), ±1 dB error only up to 500 MHz | Optimized for handheld RF field strength meters; lacks dc coupling, differential inputs, and on-chip attenuator | Select AD8307ARZ for battery-powered portable instruments needing wider RF bandwidth but accepting reduced dc accuracy and no cascade capability |
| LT5537ESC6#TRMPBF | 3–1000 MHz range, 60 dB dynamic range, 0.5 V/decade output, integrated 50 Ω input matching, no dc coupling | Designed for cellular/WiFi front-ends; requires external ac-coupling and has no guaranteed dc or low-frequency performance | Select LT5537ESC6#TRMPBF for high-frequency communications test equipment where dc response and differential signaling are not required |
Compared with AD640JNZ, AD8307ARZ offers higher RF bandwidth but sacrifices dc coupling, differential interface, and absolute calibration stability over temperature; LT5537ESC6#TRMPBF provides broader RF coverage but lacks dc-to-baseband support and military-grade accuracy-making AD640JNZ uniquely suited for precision instrumentation demanding traceable logarithmic conversion from DC.
Availability
AD640JNZ is available at Aetrix Electronics and suitable for radar IF receivers, ultrasonic time-of-flight sensors, and precision RF power meters requiring stable component supply across extended production cycles.
Supply support for AD640JNZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD640JNZ belongs to Analog Devices' precision logarithmic amplifier product line, engineered specifically for wide-dynamic-range RF/IF signal compression in defense, instrumentation, and industrial sensing applications where absolute amplitude accuracy and temperature stability are critical.
FAQ
What is the guaranteed DC accuracy of the AD640JNZ over its commercial temperature range?
The AD640JNZ guarantees total absolute DC accuracy of ±1.0 dB for input voltages from ±0.75 mV to ±200 mV across 0°C to +70°C. This includes contributions from slope error, intercept drift, and nonlinearity-verified per Analog Devices' AD640J datasheet Rev. D, Table "TOTAL ABSOLUTE DC ACCURACY". The AD640JNZ achieves this via laser trimming and on-chip bias regulation, ensuring repeatable performance without user calibration.
Can the AD640JNZ operate with single-ended inputs, or is differential input mandatory?
The AD640JNZ is designed for fully differential operation: SIG+IN (Pin 1) and SIG–IN (Pin 20) form a matched pair with 500 kΩ || 2 pF input impedance. While single-ended use is possible by grounding one input, it degrades CMRR, increases offset, and voids guaranteed AC linearity specs. For optimal performance-including ±1 dB accuracy and 145 MHz bandwidth-the AD640JNZ must be driven differentially per Figure 24 in the official datasheet.
How does the on-chip 20 dB attenuator affect intercept calibration and temperature stability?
When enabled (via pins 2–5), the AD640JNZ's on-chip attenuator shifts the intercept to 10 mV dc (–24 dBm for sine waves) and applies +0.30%/°C temperature compensation to maintain intercept stability across 0°C to +70°C. To activate this mode, Pin 8 (ITC) must be grounded-disabling internal temperature compensation-so the attenuator's TC dominates. This configuration eliminates lateral shift in the transfer curve, preserving full 50 dB dynamic range at all temperatures.
What is the maximum input voltage the AD640JNZ can handle without damage or clipping?
The AD640JNZ absolute maximum input voltage is ±300 mV (Pin 1 or Pin 20 to COM), per its Absolute Maximum Ratings table. With the on-chip 20 dB attenuator enabled, the safe input range extends to ±4 V (Pin 5 to Pin 3/4). Exceeding these limits risks permanent damage. For reliable operation within spec, inputs should remain ≤±200 mV (direct) or ≤±2 V (attenuated) to maintain ±1 dB logarithmic accuracy and avoid stage saturation.
Is the AD640JNZ pin-compatible with other variants like AD640B or AD640T?
Yes-the AD640JNZ shares identical pinout, package footprint (20-lead plastic DIP), and electrical interface with AD640B (industrial temp) and AD640T (military temp) variants. All three are drop-in replacements in terms of PCB layout and signal routing. However, temperature specifications differ: AD640JNZ is rated 0°C to +70°C, while AD640B covers –40°C to +85°C and AD640T –55°C to +125°C. Performance parameters (e.g., offset drift, slope stability) scale accordingly per datasheet tables.
AD640JNZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Logarithmic
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- -
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 350 MHz
- Current - Input Bias:
- 7 µA
- Voltage - Input Offset:
- 50 µV
- Current - Supply:
- 35mA
- Current - Output / Channel:
- 2.3 mA
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 15 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 20-PDIP
AD640JNZ FAQ
1.How can I place an order for AD640JNZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD640JNZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD640JNZ reliable?
The price and inventory of AD640JNZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD640JNZ is usually 5 days.
3.What payment methods are accepted for AD640JNZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD640JNZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD640JNZ?
AD640JNZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD640JNZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD640JNZ?
For technical support, including AD640JNZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD640JNZ requirements.
6.How does Aetrix verify that AD640JNZ is sourced from the original manufacturer or authorized distributors?
All AD640JNZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD640JNZ meets industry standards.
7.What is the process for return or replacement of AD640JNZ?
All AD640JNZ units undergo pre-shipment inspection (PSI). If there is an issue with AD640JNZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD640JNZ part is unused and in its original packaging.
Return procedure for AD640JNZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD640JNZ Tags
-
LM358DT
STMicroelectronics
-
LM358DR
Texas Instruments
-
LM2904DR
Texas Instruments
-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments
-
MCP6006T-E/OT
Microchip Technology
-
MCP6006UT-E/OT
Microchip Technology
-
LM324PWR
Texas Instruments
-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments
-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
