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Analog Devices Inc. AD6600AST
- Part No.:
- AD6600AST
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 44-LQFP
- Datasheet:
-
AD6600AST.pdf
- Description:
- IC ADC DUAL W/RSSI 44-LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:5,507
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Product details
Overview
AD6600AST from Analog Devices is a dual-channel, gain-ranging 11-bit analog-to-digital converter (ADC) with integrated RSSI detection and 2× clock output, designed for direct IF sampling in cellular/PCS base station receivers. It supports 70–250 MHz analog inputs, delivers 20 MSPS in single-channel mode or 10 MSPS per channel in diversity mode, and achieves >90 dB total signal range via 30 dB AGC + 60 dB ADC resolution. It operates from a single 5 V supply with 3.3 V or 5 V digital outputs and is specified over –40°C to +85°C.
For engineers reviewing the AD6600AST datasheet, AD6600AST pinout, AD6600AST application, or AD6600AST equivalent, key selection considerations include its dual IF input architecture, automatic gain-ranging across three RSSI-controlled attenuation ranges (0/–12/–24 dB), 450 MHz analog bandwidth, CMOS-compatible two's complement digital outputs, and compatibility with external LC resonant filters at the FLT/FLT port.
Technical Context
The AD6600AST implements a dual-path analog front end with independent 1 GHz input amplifiers and phase-compensated step attenuators per channel, feeding into a shared 450 MHz track-and-hold and 11-bit ADC core. Its gain-ranging logic uses a high-speed synchronous peak detector and 3-bit RSSI word to dynamically select attenuation and amplifier gain (12 dB or 18 dB) on a clock-by-clock basis.
Digital timing is synchronized by differential ENC/ENC inputs driving internal encode logic that generates CLK2× (2× encode rate), AB_OUT (channel A/B flag), and 11-bit D10–D0 plus 3-bit RSSI[2:0] outputs-all in two's complement format. Output voltage levels are configurable for DVCC = 3.3 V or 5 V, with rise/fall times under 8.4 ns and 10 pF load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 11-bit ADC + 3-bit RSSI exponent - enables floating-point-like dynamic range management |
| Sampling Rate | 20 MSPS (single-channel) or 10 MSPS/channel (diversity) - supports wideband IF digitization without undersampling |
| Analog Input Range | 2.0–2.86 Vp-p differential (70–250 MHz) - matches common SAW filter outputs |
| Total Signal Range | >90 dB - achieved via 30 dB AGC + 60 dB ADC, enabling reception of weak and strong signals simultaneously |
| Channel Isolation | 45–50 dB (70–250 MHz) - ensures minimal crosstalk in diversity antenna systems |
| Power Dissipation | 775 mW typical (AVCC = 5 V, DVCC = 3.3 V) - optimized for dense RF receiver card layouts |
| Supply Voltages | AVCC = 4.75–5.25 V; DVCC = 3.0–5.25 V - supports mixed-voltage digital interfacing |
Pinout & Package
AD6600AST is housed in a 44-lead LQFP (ST-44) package, surface-mount, low-profile plastic flatpack, rated for industrial temperature range (–40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN / AIN | Differential analog input Channel A | Accepts 70–250 MHz IF signals; 1 GHz bandwidth, 200 Ω nominal differential impedance |
| BIN / BIN | Differential analog input Channel B | Independent second IF path for diversity or dual-signal acquisition |
| ENC / ENC | Differential encode clock input | Drives sampling; requires AC-coupled 0.4 Vp-p differential signal at 6–20 MSPS |
| FLT / FLT | Resonant port for external LC noise filter | 630 Ω differential resistance; used to tune filter center frequency and bandwidth for IF rejection |
| D10–D0 | 11-bit two's complement ADC output | CMOS-compatible; directly interfaces to 3.3 V or 5 V DSP/FPGA without level-shifting |
| RSSI[2:0] | 3-bit received signal strength indicator | Encodes current attenuation/gain state; used for closed-loop AGC control in host system |
| AB_OUT | Channel A/B status flag | High = Channel A active; Low = Channel B active - essential for time-multiplexed diversity operation |
| CLK2× | 2× encode clock output | Synchronized to ENC; used to clock downstream digital filters (e.g., AD6620) with precise timing margins |
| A_SEL / B_SEL | Channel mode select inputs | Hard-wired to AVCC (A only) or GND (B only) to force single-channel operation |
| AVCC / DVCC / GND | Analog/digital power and ground | Separate AVCC (5 V) and DVCC (3.3 V or 5 V) supplies minimize noise coupling between analog and digital domains |
Key Features
| Feature | Design Value |
|---|---|
| Dual IF input structure with independent gain-ranging | Enables true antenna diversity or simultaneous dual-IF processing without external switching or gain control circuitry |
| Integrated 3-bit RSSI with 6 dB gain steps and hysteresis | Provides deterministic, noise-immune AGC decision points-eliminates flicker in RSSI transitions near threshold |
| 450 MHz analog input bandwidth with 1 GHz front-end amplifiers | Supports wide instantaneous bandwidth capture up to 250 MHz IF while preserving SNR and linearity |
| Two's complement CMOS digital outputs with dual-voltage support | Direct interface to both 3.3 V and 5 V logic families-reduces BOM count and layout complexity |
| On-chip 2× clock generator with sub-ns timing alignment | Delivers precisely timed CLK2× output referenced to ENC edges-enables zero-jitter synchronization with downstream filters |
Applications
| GSM/CDMA Base Station Receiver | Wireless Local Loop (WLL) Diversity Front End |
|---|---|
Use Scenario: Digitizing dual IF outputs from SAW-filtered downconverters in multi-carrier cellular base stations. IC Role / Device Role / Timing Role: Dual-channel IF sampling ADC with real-time gain-ranging and RSSI feedback for automatic signal-level adaptation. Use Value: Maintains >55 dB SNR across –12 dBFS to –42 dBFS input range, enabling reliable demodulation of adjacent channels under varying RF conditions. | Use Scenario: Receiving co-located but uncorrelated signals from two spatially separated antennas in fixed-access wireless infrastructure. IC Role / Device Role / Timing Role: Diversity sampler providing time-synchronized A/B channel data and AB_OUT flag for selection logic. Use Value: 45–50 dB channel isolation prevents cross-talk; 10 MSPS/channel sampling preserves symbol timing integrity for OFDM and QAM waveforms. |
| PCS Multi-Standard Receiver Platform | Proprietary Air Interface IF Digitizer |
Use Scenario: Supporting GSM, IS-136, and CDMA air interfaces on a single hardware platform via software-defined configuration. IC Role / Device Role / Timing Role: Programmable IF ADC with selectable attenuation ranges and flexible digital output voltage (DVCC = 3.3 V or 5 V). Use Value: Single-component solution eliminates need for discrete gain stages and level shifters-reducing PCB area and calibration effort across standards. | Use Scenario: Capturing custom-modulated IF signals in licensed-band point-to-point links where spectral purity and dynamic range are critical. IC Role / Device Role / Timing Role: High-linearity ADC with >65 dBc third-harmonic suppression at 200 MHz and 250 MHz inputs. Use Value: Attenuator 3OIP of +33 dBm ensures clean digitization of high-power IF signals without front-end compression or distortion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel IF sampling ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD6620 | Digital receive signal processor (not ADC); requires companion ADC like AD6600AST; adds 10–25 dB processing gain | Used downstream of AD6600AST for channel filtering, decimation, and AGC refinement-not a standalone replacement | Select AD6620 only when additional digital filtering and programmable gain are required post-ADC |
| AD9235BCPZ-20 | Single-channel, 12-bit, 20 MSPS ADC; no integrated RSSI, gain-ranging, or dual-input structure | Lacks diversity support and automatic gain control; requires external AGC loop and dual ADCs for comparable functionality | Choose only for cost-sensitive, single-IF designs where full AD6600AST feature set is unnecessary |
Compared with AD6600AST, AD6620 extends signal processing digitally but depends on AD6600AST for analog capture, while AD9235BCPZ-20 offers higher resolution but omits all gain-ranging, dual-channel, and RSSI capabilities-making it unsuitable for diversity or wide-dynamic-range IF sampling without significant external circuitry.
Availability
AD6600AST is available at Aetrix Electronics and suitable for GSM/CDMA base station receivers, wireless local loop diversity front ends, PCS multi-standard receiver platforms, and proprietary air interface IF digitizers requiring stable component supply and long-term industrial temperature support.
Supply support for AD6600AST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, and instrumentation markets since 1965.
The AD6600 product line was engineered specifically for cellular and PCS base station IF digitization-integrating analog gain control, high-speed conversion, and digital interface logic into a single IC to simplify receiver design and improve dynamic range consistency.
FAQ
What is the maximum analog input frequency supported by the AD6600AST?
The AD6600AST supports analog input frequencies from 70 MHz to 250 MHz, with a 450 MHz analog input 3 dB bandwidth determined by its internal track-and-hold circuit. At 250 MHz, it maintains a differential input voltage range of 2.86 Vp-p and full-scale input power of 7.7 dBm, ensuring robust performance across the entire specified IF band. The AD6600AST front-end amplifiers operate up to 1 GHz, but system-level performance is validated and guaranteed only within the 70–250 MHz range.
How does the AD6600AST implement automatic gain-ranging?
The AD6600AST implements automatic gain-ranging using an on-chip high-speed synchronous peak detector that monitors signal amplitude on both A and B channels. This drives 3-bit RSSI logic which selects among three attenuation states (0 dB, –12 dB, –24 dB) and two gain amplifier settings (+12 dB or +18 dB) on a clock-by-clock basis. Each RSSI step spans 6 dB with 6 dB hysteresis to prevent oscillation near threshold boundaries, enabling stable SNR maintenance over >90 dB input dynamic range.
Can the AD6600AST operate with a 3.3 V digital supply only?
No-the AD6600AST requires AVCC = 4.75–5.25 V for its analog circuitry, but DVCC may be set to either 3.3 V or 5.0 V to match downstream logic. Digital outputs (D10–D0, RSSI[2:0], AB_OUT, CLK2×) are CMOS-compatible and fully specified at both DVCC voltages. Operating DVCC at 3.3 V reduces total power dissipation and simplifies interface to modern 3.3 V FPGAs and DSPs, while AVCC must remain at 5 V to ensure proper analog performance.
What is the purpose of the FLT and FLT pins on the AD6600AST?
The FLT and FLT pins on the AD6600AST form a differential resonant port connected to an external LC noise filter. This filter is placed between the gain amplifier and track-and-hold stage to suppress out-of-band noise and harmonics before sampling. With a nominal differential resistance of 630 Ω and capacitance of 1.75 pF, the FLT/FLT port allows precise tuning of filter center frequency and bandwidth-critical for meeting adjacent channel rejection requirements in GSM, CDMA, and WLL applications.
Is the AD6600AST pin-compatible with other members of the AD66xx family?
No-the AD6600AST has a unique 44-lead LQFP pinout optimized for its dual-channel, gain-ranging architecture and is not pin-compatible with AD6620 (digital processor), AD6630 (IF amplifier), or other AD66xx converters. Pin assignments-including dedicated A_SEL/B_SEL mode controls, dual FLT ports, and AB_OUT flag-are specific to the AD6600AST. Migration to alternate parts requires PCB redesign and firmware adaptation due to fundamental differences in signal routing and control logic.
AD6600AST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 44-LQFP
- Packaging:
- Bag
- Product Status:
- Obsolete
- Number of Bits:
- 11
- Sampling Rate (Per Second):
- 20M
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- Parallel
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 1
- Architecture:
- -
- Reference Type:
- -
- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 44-LQFP (10x10)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD6600AST FAQ
1.How can I place an order for AD6600AST through Aetrix?
Please submit a Request for Quotation (RFQ) for AD6600AST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD6600AST reliable?
The price and inventory of AD6600AST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD6600AST is usually 5 days.
3.What payment methods are accepted for AD6600AST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD6600AST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD6600AST?
AD6600AST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD6600AST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD6600AST?
For technical support, including AD6600AST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD6600AST requirements.
6.How does Aetrix verify that AD6600AST is sourced from the original manufacturer or authorized distributors?
All AD6600AST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD6600AST meets industry standards.
7.What is the process for return or replacement of AD6600AST?
All AD6600AST units undergo pre-shipment inspection (PSI). If there is an issue with AD6600AST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD6600AST part is unused and in its original packaging.
Return procedure for AD6600AST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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