Analog Devices Inc. AD6600ASTZ-REEL
- Part No.:
- AD6600ASTZ-REEL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 44-LQFP
- Datasheet:
-
AD6600ASTZ-REEL.pdf
- Description:
- IC ADC 11BIT PIPELINED 44LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,072
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Product details
Overview
AD6600ASTZ-REEL from Analog Devices is a dual-channel, gain-ranging 11-bit analog-to-digital converter with integrated RSSI detection, designed for direct IF sampling in cellular/PCS base station receivers. It supports 70–250 MHz analog inputs, delivers 20 MSPS in single-channel mode or 10 MSPS per channel in diversity mode, and achieves >100 dB total signal range via 30 dB AGC + 60 dB ADC dynamic range. It operates from a single 5 V supply with 3.3 V or 5 V digital outputs and is used in GSM, CDMA, and wireless local loop systems.
For engineers reviewing the AD6600ASTZ-REEL datasheet, AD6600ASTZ-REEL pinout, AD6600ASTZ-REEL application, or AD6600ASTZ-REEL equivalent, key selection criteria include its dual IF input architecture, 450 MHz track-and-hold bandwidth, 11-bit two's complement output format, 3-bit RSSI word, A/B channel indicator, and compatibility with external resonant LC filters at the FLT pins.
Technical Context
The AD6600ASTZ-REEL implements a dual-path analog front end with independent 0 dB/–12 dB/–24 dB step attenuators per channel, followed by a 12 dB/18 dB programmable gain amplifier and a shared 450 MHz track-and-hold stage. Its gain-ranging logic uses real-time peak detection to switch attenuation and gain settings on a clock-by-clock basis, enabling automatic maintenance of optimal ADC input level across >90 dB input power variation.
Digital timing is synchronized to differential ENC/ENC inputs, generating an internal 2× clock (CLK2×) for data capture. Output signals - D10:D0 (11-bit two's complement), RSSI[2:0], AB_OUT, and CLK2× - are CMOS-compatible and support either 3.3 V or 5 V DVCC, with rise/fall times under 8.4 ns (data) and 3 ns (CLK2×) at 10 pF load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 11-bit ADC + 3-bit RSSI exponent: enables floating-point-like dynamic range compression for wide-input-signal applications. |
| Sampling Rate | 20 MSPS (single-channel) or 10 MSPS/channel (diversity): defines maximum symbol rate support for multi-carrier or dual-antenna systems. |
| Analog Input Bandwidth | 450 MHz (track-and-hold limited): supports direct sampling up to 250 MHz IF with minimal aliasing risk. |
| Total Signal Range | >100 dB after processing gain: achieved via 30 dB AGC range + 60 dB ADC SNR, critical for weak-signal reception in noisy RF environments. |
| Channel Isolation | ≥45 dB (70–250 MHz): ensures minimal crosstalk between antenna paths in diversity receiver architectures. |
| Power Dissipation | 775 mW typical (AVCC = 5 V, DVCC = 3.3 V): informs thermal design and power supply sizing for dense base station PCB layouts. |
| RSSI Hysteresis | 6 dB digital hysteresis: prevents rapid toggling of gain-range decisions near threshold points due to noise or amplitude fluctuations. |
Pinout & Package
AD6600ASTZ-REEL is housed in a 44-lead LQFP (Low-Profile Quad Flatpack), surface-mount package, specified for industrial temperature operation (–40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DVCC (Pins 1, 33) | Digital power supply | Supplies 3.3 V or 5 V to all digital outputs (D10:D0, RSSI[2:0], AB_OUT, CLK2×); decoupling required for noise-sensitive digital interface. |
| AVCC (Pins 4, 14, 15, 18, 20, 25, 31) | Analog power supply | 5 V supply for analog front end, gain stages, and track-and-hold; separate from DVCC to minimize digital noise coupling into analog path. |
| AIN / AIN, BIN / BIN (Pins 11, 12, 22, 23) | Differential analog inputs | Two fully independent IF input ports; each accepts 70–250 MHz differential signals with 2.0–2.86 Vp-p full-scale range depending on frequency. |
| FLT / FLT (Pins 16, 17) | Resonant filter port | Connects to external LC network (630 Ω nominal differential impedance); sets noise-filter bandwidth and gain peaking before track-and-hold. |
| ENC / ENC (Pins 26, 27) | Differential encode clock input | Drives sampling timing; requires AC-coupled differential drive with ≥20 ns pulse width and 50% duty cycle for rated performance. |
| D10–D0 (Pins 34–44) | Digital data output | 11-bit two's complement ADC output; LSB-aligned, CMOS-compatible, directly interfaces to 3.3 V or 5 V DSP/FPGA without level-shifting. |
| RSSI[2:0] (Pins 6–8) | RSSI exponent output | 3-bit digital word indicating current gain-range setting; used for external AGC control or signal strength monitoring. |
| AB_OUT (Pin 29) | Channel identifier flag | Logic-high = Channel A active, logic-low = Channel B active; essential for time-multiplexed diversity or dual-IF system synchronization. |
| A_SEL / B_SEL (Pins 9, 10) | Input channel select | Hard-wired to AVCC (A_SEL) or GND (B_SEL) to configure single-channel operation; both grounded for diversity mode. |
Key Features
| Feature | Design Value |
|---|---|
| Dual IF input structure with independent gain-ranging | Enables simultaneous sampling of two antennas (diversity) or two independent IF signals without external switching or gain control circuitry. |
| Integrated 450 MHz track-and-hold + 11-bit ADC | Eliminates need for external sample-hold or high-speed ADC, reducing board area and signal integrity challenges in IF sampling designs. |
| On-chip 3-bit RSSI with 6 dB hysteresis | Provides real-time received signal strength indication with stable range transitions, simplifying closed-loop AGC implementation in baseband processors. |
| 2× clock output (CLK2×) referenced to ENC | Delivers deterministic timing for downstream digital filtering (e.g., with AD6620), removing need for external clock doublers or PLLs. |
| External resonant LC filter interface (FLT/FLT) | Allows precise tuning of anti-alias and noise-filter response at IF frequency, improving SNR and adjacent-channel rejection without fixed-component constraints. |
| CMOS-compatible digital outputs with dual-voltage support | Interfaces directly to 3.3 V or 5 V logic families (e.g., ADSP-BF533, TI C64x), avoiding level translators and reducing BOM count and layout complexity. |
Applications
| GSM Base Station Receiver | CDMA Diversity Front End |
|---|---|
Use Scenario: Digitizing dual IF outputs from SAW-filtered downconverters in a macrocell BTS supporting multiple GSM carriers. IC Role / Device Role / Timing Role: Dual-channel IF sampling ADC with automatic gain-ranging, providing 11-bit I/Q data and RSSI feedback to baseband processor. Use Value: Achieves >100 dB dynamic range across –90 dBm to –10 dBm input levels, enabling reliable demodulation of weak and strong co-channel signals without manual gain adjustment. |
Use Scenario: Simultaneous sampling of two antenna paths in a CDMA base station to mitigate multipath fading using selection or combining diversity. IC Role / Device Role / Timing Role: Dual-path gain-ranging ADC delivering time-aligned 10 MSPS/channel data streams with AB_OUT flag for path identification. Use Value: Provides ≥45 dB channel isolation and <0.5° phase matching across 70–250 MHz, preserving relative signal phase for coherent diversity combining algorithms. |
| Wireless Local Loop (WLL) Fixed Access | TDMA Multi-Channel IF Digitizer |
Use Scenario: IF digitization in point-to-multipoint WLL subscriber units operating in 2.4 GHz or 5.8 GHz bands with IF at 140–220 MHz. IC Role / Device Role / Timing Role: Stand-alone IF sampling ADC with integrated RSSI and 2× clock output, interfacing directly to FPGA-based demodulator. Use Value: Delivers 55 dB SNR at 150 MHz and –1 dBFS, supporting high-order QAM constellations (e.g., 64-QAM) in spectrally efficient fixed-access links. |
Use Scenario: Time-division multiplexed sampling of multiple IF channels in a TDMA repeater or hub station using shared ADC resources. IC Role / Device Role / Timing Role: Single-channel 20 MSPS ADC with A/B select pins configured for rapid channel switching between time slots. Use Value: Enables 20 MSPS sampling of up to four IF channels (5 MSPS each) via external analog MUX and A_SEL/B_SEL control, reducing component count vs. discrete ADCs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel IF sampling ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD6620 + AD6600 | AD6620 is a companion digital receive signal processor; not a drop-in replacement but a functional extension adding 10–25 dB processing gain and digital filtering. | Used downstream of AD6600ASTZ-REEL to enhance SNR and perform channelization; requires additional PCB space and interface logic. | Select AD6620 only when >100 dB effective dynamic range or programmable digital filtering is required beyond AD6600ASTZ-REEL's analog-domain capabilities. |
| AD9236BCPZ-80 | Single-channel, 12-bit, 80 MSPS ADC with no integrated AGC, RSSI, or dual-input structure; requires external gain control and IF conditioning. | Suitable for high-speed single-IF applications (e.g., broadband wireless access), but lacks diversity support and automatic range adaptation. | Choose AD9236BCPZ-80 only for non-diversity, higher-sample-rate (>20 MSPS) systems where external AGC and signal conditioning are already implemented. |
Compared with AD6620 + AD6600 (a cascaded solution) and AD9236BCPZ-80 (a higher-speed single-channel alternative), AD6600ASTZ-REEL uniquely integrates dual IF inputs, gain-ranging, RSSI, and 2× clock generation in one 44-lead LQFP package-reducing system-level complexity and component count for cellular infrastructure receivers.
Availability
AD6600ASTZ-REEL is available at Aetrix Electronics and suitable for GSM base station receivers, CDMA diversity front ends, wireless local loop fixed access units, and TDMA multi-channel IF digitizers requiring stable component supply and long-term industrial temperature support.
Supply support for AD6600ASTZ-REEL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD6600ASTZ-REEL belongs to Analog Devices' high-speed receiver IC product line, engineered specifically for cellular and PCS infrastructure applications requiring wide dynamic range, dual-antenna support, and direct IF sampling capability.
FAQ
What is the maximum analog input frequency supported by the AD6600ASTZ-REEL?
The AD6600ASTZ-REEL supports analog input frequencies from 70 MHz to 250 MHz, with a 450 MHz analog input 3 dB bandwidth determined by its internal track-and-hold circuit. Full-scale performance (e.g., SNR, distortion) is guaranteed across this 70–250 MHz range, and the device remains unconditionally stable within it. Operation above 250 MHz is not characterized or supported.
How does the gain-ranging function work in the AD6600ASTZ-REEL?
The AD6600ASTZ-REEL implements automatic gain-ranging using on-chip peak detectors that monitor signal amplitude on both input channels. Based on detected level, it dynamically selects among three attenuation states (0 dB, –12 dB, –24 dB) and two gain settings (+12 dB, +18 dB) on a clock-by-clock basis. This maintains optimal ADC input level across >90 dB input power variation, delivering consistent SNR without external control loops.
Can the AD6600ASTZ-REEL operate with a 3.3 V digital supply?
Yes - the AD6600ASTZ-REEL supports DVCC = 3.3 V (or 5 V) for its digital outputs (D10:D0, RSSI[2:0], AB_OUT, CLK2×). When DVCC = 3.3 V, logic "1" output voltage is guaranteed ≥2.8 V and logic "0" ≤0.5 V, ensuring compatibility with standard 3.3 V CMOS logic families. AVCC must remain at 5 V for analog functionality.
What is the purpose of the FLT and FLT pins on the AD6600ASTZ-REEL?
The FLT and FLT pins form a differential resonant port connecting to an external LC network. This network acts as a tunable noise filter and gain-peaking stage preceding the track-and-hold, allowing designers to optimize anti-aliasing and SNR at the target IF frequency (e.g., 150 MHz or 200 MHz). The nominal differential impedance is 630 Ω, and capacitance is 1.75 pF.
Is the AD6600ASTZ-REEL pin-compatible with other members of the AD66xx family?
No - the AD6600ASTZ-REEL has a unique 44-lead LQFP pinout optimized for its dual-channel, gain-ranging architecture. It is not pin-compatible with AD6620, AD6630, or other AD66xx devices. Pin assignments for analog inputs (AIN/AIN, BIN/BIN), encode (ENC/ENC), digital outputs (D10:D0), and control signals (A_SEL, B_SEL, AB_OUT) are specific to the AD6600ASTZ-REEL and require dedicated PCB layout.
AD6600ASTZ-REEL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 44-LQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 11
- Sampling Rate (Per Second):
- 20M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- Parallel
- Configuration:
- MUX-S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 3V ~ 5.25V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 44-LQFP (10x10)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD6600ASTZ-REEL FAQ
1.How can I place an order for AD6600ASTZ-REEL through Aetrix?
Please submit a Request for Quotation (RFQ) for AD6600ASTZ-REEL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD6600ASTZ-REEL reliable?
The price and inventory of AD6600ASTZ-REEL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD6600ASTZ-REEL is usually 5 days.
3.What payment methods are accepted for AD6600ASTZ-REEL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD6600ASTZ-REEL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD6600ASTZ-REEL?
AD6600ASTZ-REEL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD6600ASTZ-REEL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD6600ASTZ-REEL?
For technical support, including AD6600ASTZ-REEL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD6600ASTZ-REEL requirements.
6.How does Aetrix verify that AD6600ASTZ-REEL is sourced from the original manufacturer or authorized distributors?
All AD6600ASTZ-REEL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD6600ASTZ-REEL meets industry standards.
7.What is the process for return or replacement of AD6600ASTZ-REEL?
All AD6600ASTZ-REEL units undergo pre-shipment inspection (PSI). If there is an issue with AD6600ASTZ-REEL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD6600ASTZ-REEL part is unused and in its original packaging.
Return procedure for AD6600ASTZ-REEL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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