Analog Devices Inc. AD6644AST-40
- Part No.:
- AD6644AST-40
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-LQFP
- Datasheet:
-
AD6644AST-40.pdf
- Description:
- IC ADC 14BIT 40MSPS 52-LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:37,757
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD6644AST-40 from Analog Devices is a 14-bit, 40 MSPS monolithic analog-to-digital converter (ADC) with differential analog inputs, 100 dB two-tone SFDR, 74 dB SNR at 2.2 MHz, and 250 MHz analog input bandwidth. It integrates on-chip track-and-hold and 2.4 V reference, and targets IF sampling in multichannel digital receivers.
For engineers reviewing the AD6644AST-40 datasheet, AD6644AST-40 pinout, AD6644AST-40 application, or AD6644AST-40 equivalent, this page delivers verified specifications, validated pin functions, confirmed LQFP-52 package mapping, real-world communication receiver use cases, and two technically documented alternative ADCs for multimode baseband and IF digitization.
Technical Context
The AD6644AST-40 employs a three-stage subrange architecture with pipelined track-and-hold stages (TH1–TH5), 5-bit coarse ADC1 + DAC1 (laser-trimmed), 5-bit ADC2 + DAC2, and final 6-bit ADC3 - all coordinated by digital error correction logic to deliver 14-bit twos complement output. Its differential ENCODE/ENCODE interface requires <300 fs sampling jitter for rated performance.
It operates with AVCC = 5 V (analog supply) and DVCC = 3.3 V (digital supply), supports 15–40 MSPS conversion rates, and features CMOS-compatible outputs with DRY (data-ready) and OVR (overrange) status signals. The analog input stage accepts ±0.55 V differential swing around 2.4 V common-mode, yielding 2.2 V p-p full-scale range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - guarantees monotonicity and no missing codes across full temperature range. |
| Sample Rate | 40 MSPS - maximum guaranteed conversion rate for parametric compliance at −25°C to +85°C. |
| Two-Tone SFDR | 100 dBFS - spurious-free dynamic range measured with 15 MHz / 15.5 MHz tones at −7 dBFS, enabling clean wideband signal capture. |
| Analog Input Bandwidth | 250 MHz - usable frequency range before −3 dB roll-off, supporting direct IF sampling up to cellular/WCDMA bands. |
| Power Dissipation | 1.3 W - total consumption (IAVCC = 276 mA @ 5 V, IDVCC = 36 mA @ 3.3 V), optimized for high-speed mixed-signal systems. |
| Aperture Jitter | 0.2 ps rms - enables >74 dB SNR at 30.5 MHz input without external clock conditioning. |
| Digital Output Format | Twos complement - simplifies FPGA/ASIC interface with standard signed integer arithmetic and no post-processing. |
Pinout & Package
AD6644AST-40 is housed in a 52-lead plastic low-profile quad flat package (LQFP), RoHS-compliant, rated for −25°C to +85°C ambient operation. Thermal resistance θJA = 33°C/W on a 6-layer PCB with solid ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN / AIN | Differential analog input pair | Accepts ±0.55 V swing around 2.4 V common-mode; 1 kΩ differential resistance, 1.5 pF capacitance - requires matched layout and transformer/capacitive AC coupling. |
| ENCODE / ENCODE | Differential encode clock inputs | Trigger conversion on rising edge; require <300 fs jitter and 50% duty cycle for rated SFDR; internally biased, no external termination needed. |
| D0–D13 | Parallel digital output bus | 14-bit twos complement CMOS outputs (3.3 V compatible); D0 = LSB, D13 = MSB; timing-critical - must meet tE_FL ≤ 9.2 ns hold/setup windows. |
| DRY | Data-ready strobe | Inverted, delayed version of ENCODE; indicates valid data window - used for latching D0–D13 in synchronous logic. |
| OVR | Overrange flag | Active-high signal indicating analog input exceeded ±FS range; enables real-time clipping detection in receiver AGC loops. |
| VREF | 2.4 V analog reference output | Stable internal voltage source; must be bypassed with 0.1 µF microwave capacitor to GND for noise suppression. |
| DMID | Digital output midpoint reference | ≈DVCC/2 (1.65 V); provides common-mode level for interfacing to 3.3 V CMOS receivers. |
| AVCC / DVCC / GND | Power and ground terminals | Separate 5 V analog (AVCC) and 3.3 V digital (DVCC) supplies; 24 dedicated GND pins minimize ground bounce and improve PSRR. |
Key Features
| Feature | Design Value |
|---|---|
| On-chip track-and-hold + reference | Eliminates need for external TH circuitry or precision voltage reference ICs - reduces BOM count and layout sensitivity. |
| Pin compatibility with AD6645 | Enables drop-in upgrade path to higher-speed 13-bit variant (65 MSPS) without PCB redesign or firmware changes. |
| Differential analog and encode interfaces | Rejects common-mode noise and EMI in RF front-ends; supports transformer-coupled IF inputs typical in GSM/CDMA base stations. |
| 100 dB two-tone SFDR | Supports simultaneous reception of multiple closely spaced carriers in software-defined radios without analog pre-filtering. |
| 3.3 V CMOS digital outputs | Direct interface to Xilinx Virtex FPGAs or ASICs without level-shifting - simplifies timing closure and reduces power. |
Applications
| AMPS/IS-136 Base Station Receiver | WCDMA Node B IF Digitizer |
|---|---|
Use Scenario: Digitizing 45 MHz IF signals from multi-carrier AMPS/IS-136 channelizers prior to digital downconversion and demodulation. IC Role / Device Role / Timing Role: High-linearity IF sampling ADC providing 14-bit resolution and 100 dB SFDR to preserve adjacent-channel interference margin. Use Value: Enables single-chip digitization of up to 4 simultaneous voice channels within 1.25 MHz bandwidth, reducing analog filter complexity and calibration overhead. |
Use Scenario: Capturing 190 MHz WCDMA IF output from quadrature mixer in macrocell Node B transceiver. IC Role / Device Role / Timing Role: Wideband ADC with 250 MHz analog bandwidth and low aperture jitter, synchronizing to 40 MSPS system clock for 5 MHz channel processing. Use Value: Maintains EVM < 8% under 64-QAM modulation by preserving SNR > 73 dB across 30.5 MHz input tone - critical for 3GPP R99 compliance. |
| Radar Pulse-Doppler Processor | Communications Test Instrumentation |
Use Scenario: Sampling intermediate frequency outputs from pulsed radar receivers operating at L-band (1–2 GHz) with 10–50 MHz IF bandwidth. IC Role / Device Role / Timing Role: High-SFDR ADC capturing short-duration pulses with minimal harmonic distortion to support accurate Doppler shift estimation. Use Value: 92 dBc worst-harmonic at 2.2 MHz and 85 dBc at 30.5 MHz ensures unambiguous target velocity resolution in clutter-limited environments. |
Use Scenario: Embedded digitizer in vector signal analyzer measuring spectral purity of LTE eNodeB transmitters. IC Role / Device Role / Timing Role: Reference-grade ADC validating transmitter ACLR and EVM by capturing 20 MHz LTE signals at baseband or IF. Use Value: 74.5 dB SNR and 100 dB two-tone SFDR provide measurement floor 15 dB below 3GPP conformance limits - eliminating need for external averaging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD6644AST-65 | Same die, guaranteed 65 MSPS sample rate; identical pinout, timing, and analog specs except max conversion rate and associated AC performance at higher frequencies. | Required for systems needing >40 MSPS IF sampling (e.g., wideband CDMA2000 1xEV-DO). | Select AD6644AST-65 when Nyquist zone coverage beyond 20 MHz is mandatory; AD6644AST-40 suffices for 15 MHz WCDMA or dual-IF architectures. |
| AD9240AST-40 | 14-bit, 40 MSPS ADC with 72 dB SNR (typ), 88 dB SFDR, and 105 MHz analog bandwidth; uses different architecture (folded-cascade), no integrated reference. | Suitable for cost-sensitive industrial imaging or lower-dynamic-range instrumentation where 100 dB SFDR is not required. | Choose AD9240AST-40 only if system SFDR budget allows ≥12 dB degradation; AD6644AST-40 remains preferred for telecom infrastructure due to superior linearity and integrated reference. |
Compared with AD6644AST-65, the AD6644AST-40 trades maximum sample rate for tighter thermal/power constraints while retaining identical pinout and interface logic; versus AD9240AST-40, it delivers 12 dB higher SFDR and 145 MHz wider analog bandwidth at the cost of higher power and process-specific design maturity.
Availability
AD6644AST-40 is available at Aetrix Electronics and suitable for multichannel base station receivers, WCDMA Node B IF digitizers, and radar pulse-Doppler processors requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AD6644AST-40 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.
The AD6644 belongs to Analog Devices' SoftCell® transceiver chipset family, engineered specifically for software-defined radio infrastructure - emphasizing wideband linearity, low jitter, and seamless integration with digital downconverters like the AD6620.
FAQ
What is the guaranteed maximum sample rate for AD6644AST-40?
The AD6644AST-40 is guaranteed to operate at 40 MSPS across its full temperature range (−25°C to +85°C). This is explicitly specified in Table 3 of the Rev. D datasheet under "Maximum Conversion Rate" for the AD6644AST-40 column. Performance at higher rates (e.g., 65 MSPS) applies only to the AD6644AST-65 variant.
Does AD6644AST-40 include an internal voltage reference?
Yes, the AD6644AST-40 integrates a precise 2.4 V internal reference (VREF pin), confirmed in the General Description and Pin Function Descriptions sections. It requires external 0.1 µF microwave capacitor bypassing to GND per Figure 3 and Table 8 - no external reference IC is needed for basic operation.
Is AD6644AST-40 pin-compatible with other members of the AD6644 family?
Yes, AD6644AST-40 is pin-compatible with AD6644AST-65 and functionally compatible with AD6645 per the Features section. All share identical 52-lead LQFP packaging, pin numbering, and I/O assignment - enabling hardware reuse across 40 MSPS and 65 MSPS configurations without layout changes.
What digital output format does AD6644AST-40 use?
The AD6644AST-40 outputs data in twos complement format, as stated in both the Features list and Digital Specifications table. D0 is the LSB and D13 is the MSB, with DMID providing a 1.65 V midpoint reference for interfacing to 3.3 V CMOS logic.
What is the analog input voltage range for AD6644AST-40?
The AD6644AST-40 accepts a differential analog input voltage span of 2.2 V p-p, with each input (AIN/AIN) centered at 2.4 V and swinging ±0.55 V. This is specified in Table 1 under "Differential Input Voltage Span" and confirmed in the Theory of Operation section.
AD6644AST-40 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-LQFP
- Packaging:
- Bag
- Product Status:
- Obsolete
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 40M
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- Parallel
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 4
- Architecture:
- -
- Reference Type:
- -
- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- -25°C ~ 85°C
- Supplier Device Package:
- 52-LQFP (10x10)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD6644AST-40 FAQ
1.How can I place an order for AD6644AST-40 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD6644AST-40 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD6644AST-40 reliable?
The price and inventory of AD6644AST-40 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD6644AST-40 is usually 5 days.
3.What payment methods are accepted for AD6644AST-40?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD6644AST-40 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD6644AST-40?
AD6644AST-40 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD6644AST-40 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD6644AST-40?
For technical support, including AD6644AST-40 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD6644AST-40 requirements.
6.How does Aetrix verify that AD6644AST-40 is sourced from the original manufacturer or authorized distributors?
All AD6644AST-40 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD6644AST-40 meets industry standards.
7.What is the process for return or replacement of AD6644AST-40?
All AD6644AST-40 units undergo pre-shipment inspection (PSI). If there is an issue with AD6644AST-40, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD6644AST-40 part is unused and in its original packaging.
Return procedure for AD6644AST-40:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD6644AST-40 Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

