Analog Devices Inc. AD6645ASVZ-80
- Part No.:
- AD6645ASVZ-80
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-TQFP Exposed Pad
- Datasheet:
-
AD6645ASVZ-80.pdf
- Description:
- IC ADC 14BIT PIPELINED 52TQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD6645ASVZ-80 from Analog Devices is a 14-bit, 80 MSPS analog-to-digital converter (ADC) designed for high-fidelity IF sampling in multichannel receivers. It delivers 75 dB SNR at 15 MHz input, 89 dBc SFDR at 70 MHz, and 0.1 ps rms aperture jitter, with differential analog inputs and CMOS-compatible 3.3 V digital outputs. It operates across −40°C to +85°C in base station infrastructure and radar front-ends.
For engineers reviewing the AD6645ASVZ-80 datasheet, AD6645ASVZ-80 pinout, AD6645ASVZ-80 application, or AD6645ASVZ-80 equivalent, key selection criteria include its 200 MHz analog input bandwidth, 100 dBFS two-tone SFDR performance, pin compatibility with AD6644, thermal management via exposed pad, and support for W-CDMA/CDMA multimode IF digitization.
Technical Context
The AD6645ASVZ-80 employs a multipass circuit architecture on Analog Devices' XFCB process to achieve high dynamic range across the second Nyquist band. Its track-and-hold, internal reference, and digital error correction logic are monolithically integrated to enable direct IF sampling without external signal conditioning.
It supports differential encode clocking with precise timing control (tENC = 12.5 ns), data-ready synchronization, and overrange detection. The ADC maintains 72 dB SNR up to 200 MHz input frequency and sustains 100 dBFS two-tone SFDR at 30.5 MHz - critical for multicarrier 3G receiver linearity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - provides 16,384 quantization levels for high-resolution signal capture in wideband communications. |
| Sampling Rate | 80 MSPS - enables digitization of IF signals up to 40 MHz bandwidth per Nyquist criterion. |
| SNR @ 15.5 MHz | 75.0 dB - ensures clean digitization of narrowband cellular carriers with minimal quantization noise floor. |
| Two-Tone SFDR | 100 dBFS @ 30.5/31.5 MHz - suppresses intermodulation spurs in dense multicarrier environments like W-CDMA. |
| Analog Input Bandwidth | 270 MHz - supports direct sampling of IF signals up to 200 MHz with <3 dB roll-off. |
| Aperture Jitter | 0.1 ps rms - limits sampling uncertainty-induced noise, enabling >74 dB SNR at high input frequencies. |
| Power Dissipation | 1.5 W - requires thermal design with soldered exposed pad to maintain junction temperature below 150°C. |
| Digital Interface | 3.3 V CMOS, twos complement - simplifies interface to FPGA or ASIC logic without level-shifting. |
Pinout & Package
The AD6645ASVZ-80 is housed in a 52-lead TQFP_EP (exposed pad) package. Thermal performance requires soldering the exposed paddle to PCB ground plane per JEDEC JESD51-2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN / AIN | Differential analog input | Accepts 2.2 V p-p differential signal; high-impedance (1 kΩ) and low-capacitance (1.5 pF) for minimal loading of preceding amplifier. |
| ENCODE / ENCODE | Differential sampling clock input | Initiates conversion on rising edge; requires matched trace lengths and controlled impedance (10 kΩ differential termination). |
| D0–D13 | Twos complement digital output bus | 14-bit parallel CMOS outputs (LSB to MSB); latched by DRY signal; compatible with 3.3 V logic families. |
| DRY | Data-ready strobe | Inverted, delayed version of ENCODE; used to latch D0–D13 into receiving logic with precise setup/hold timing. |
| OVR | Overrange indicator | Active-high flag signaling analog input exceeded ±FS range - enables real-time gain control or clipping mitigation. |
| VREF | 2.4 V reference output | Provides common-mode offset for dc-coupled differential amplifiers (e.g., AD8138); must be buffered if driving additional circuitry. |
| C1 / C2 | Internal reference compensation pins | Require 0.1 µF microwave capacitor to ground each; stabilize internal voltage references for optimal INL/DNL. |
| EPAD | Exposed thermal paddle | Must be soldered to solid GND plane; primary thermal path - reduces θJA to 23°C/W with zero airflow. |
Key Features
| Feature | Design Value |
|---|---|
| IF Sampling to 200 MHz | Enables direct digitization of cellular IF bands (e.g., 70–190 MHz W-CDMA) without downconversion, reducing component count and phase noise. |
| Pin Compatibility with AD6644 | Allows drop-in replacement in existing 14-bit ADC designs operating at ≤65 MSPS, easing migration to higher-speed sampling. |
| 100 dBFS Two-Tone SFDR | Reduces filtering requirements on RF front-end by suppressing IMD products - critical for software-defined radio receivers handling multiple simultaneous channels. |
| Integrated Track-and-Hold + Reference | Eliminates need for external T/H amplifier or reference buffer, minimizing board area and layout sensitivity in high-speed signal chains. |
| Exposed Pad Thermal Management | Enables reliable operation at full 80 MSPS across −40°C to +85°C ambient when EPAD is soldered to GND plane per JEDEC guidelines. |
Applications
| Base Station Receiver Front-End | Software-Defined Radio (SDR) Transceiver |
|---|---|
Use Scenario: Digitizing 70–150 MHz IF signals from multi-carrier CDMA/W-CDMA antenna arrays in macrocell base stations. IC Role / Device Role / Timing Role: High-speed ADC capturing wide instantaneous bandwidth while maintaining SFDR >90 dBc for adjacent-channel interference rejection. Use Value: Enables single-chip digitization of up to four W-CDMA carriers (e.g., 4× @ 46.08 MHz) without analog prefiltering, reducing BOM cost and calibration complexity. | Use Scenario: Flexible IF sampling in reconfigurable SDR platforms supporting AMPS, IS-136, GSM, and LTE waveforms. IC Role / Device Role / Timing Role: Core digitizer providing programmable sample rate (30–80 MSPS) and deterministic latency via DRY-synchronized output. Use Value: Supports real-time waveform switching with <1 µs reconfiguration time due to no external reference or T/H dependencies. |
| Radar Intermediate Frequency Processing | Communications Test Instrumentation |
Use Scenario: Capturing pulsed L-band (1–2 GHz) radar IF outputs after downconversion to 140–190 MHz for pulse compression and Doppler analysis. IC Role / Device Role / Timing Role: High-SNR ADC preserving signal fidelity across wide IF bandwidths (up to 200 MHz) with low aperture jitter. Use Value: Delivers 72 dB SNR at 190 MHz input - sufficient for detecting weak return pulses amid clutter without oversampling penalties. | Use Scenario: Embedded digitizer in vector signal analyzers measuring spectral purity, EVM, and ACLR of 3G/4G transmitters. IC Role / Device Role / Timing Role: Precision ADC providing calibrated, low-spur acquisition for compliance testing against 3GPP standards. Use Value: Achieves 100 dBFS two-tone SFDR - exceeds required spur-free dynamic range for ACLR measurements on 64-QAM LTE signals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD6644ASVZ-65 | 14-bit, 65 MSPS; lower power (1.1 W); reduced SFDR (85 dBc @ 70 MHz); same 52-lead TQFP_EP package. | Targeted for cost-sensitive, lower-bandwidth IF sampling where 80 MSPS is not required. | Select AD6644ASVZ-65 when system bandwidth ≤32.5 MHz and thermal budget is constrained. |
| AD9246BCPZ-80 | 14-bit, 80 MSPS; 1.8 V supply; LVDS outputs; 125 mW lower power; 2.2 V p-p input range; different pinout. | Designed for low-power, portable instrumentation with serial LVDS interface and smaller 48-lead LFCSP package. | Select AD9246BCPZ-80 when board space, power, or EMI constraints favor LVDS and compact packaging over CMOS parallel interface. |
Compared with AD6644ASVZ-65, AD6645ASVZ-80 delivers 15 MSPS higher throughput and 15 dB better SFDR at 70 MHz - essential for dense multicarrier systems. Versus AD9246BCPZ-80, AD6645ASVZ-80 offers superior SNR (75 dB vs. 72.5 dB) and proven robustness in base station thermal environments, but requires more board area and higher power.
Availability
AD6645ASVZ-80 is available at Aetrix Electronics and suitable for base station infrastructure, radar signal processing, and communications test instrumentation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AD6645ASVZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD6645ASVZ-80 belongs to Analog Devices' SoftCell® transceiver chipset family, engineered specifically for multichannel, multimode wireless infrastructure receivers demanding exceptional dynamic range and IF sampling capability.
FAQ
What is the maximum analog input frequency supported by the AD6645ASVZ-80?
The AD6645ASVZ-80 supports analog input frequencies up to 200 MHz while maintaining ≥72 dB SNR and usable SFDR. Its analog input bandwidth is specified at 270 MHz (−3 dB point), enabling high-fidelity sampling of IF signals in the second Nyquist zone for applications such as W-CDMA and radar.
Does the AD6645ASVZ-80 require external reference or track-and-hold circuitry?
No. The AD6645ASVZ-80 integrates all necessary functions - including track-and-hold, internal 2.4 V reference, and digital error correction logic - on a single die. External components are limited to decoupling capacitors on VREF, C1, C2, and power supplies; no external reference or T/H amplifier is needed.
How does the exposed pad (EPAD) of the AD6645ASVZ-80 affect thermal performance?
The exposed pad of the AD6645ASVZ-80 must be soldered to the PCB ground plane to achieve specified thermal resistance (θJA = 23°C/W). Without proper EPAD connection, junction temperature rise exceeds safe limits at 80 MSPS, risking parametric drift or reliability failure in continuous operation.
Is the AD6645ASVZ-80 pin-compatible with other members of the AD66xx family?
Yes - the AD6645ASVZ-80 shares identical pinout and footprint with the AD6644 (14-bit, 40/65 MSPS), enabling hardware reuse in legacy designs. However, it is not pin-compatible with AD6640 or AD9246 due to differing pin assignments, supply voltages, and interface types.
What digital output format does the AD6645ASVZ-80 use, and how is data synchronized?
The AD6645ASVZ-80 uses twos complement format on its 14-bit parallel CMOS outputs (D0–D13). Data is synchronized using the DRY (data-ready) signal - an inverted, delayed version of ENCODE - which provides a clean strobe for latching valid data with defined setup and hold times.
AD6645ASVZ-80 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-TQFP Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 3V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 52-TQFP-EP (10x10)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD6645ASVZ-80 FAQ
1.How can I place an order for AD6645ASVZ-80 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD6645ASVZ-80 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD6645ASVZ-80 reliable?
The price and inventory of AD6645ASVZ-80 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD6645ASVZ-80 is usually 5 days.
3.What payment methods are accepted for AD6645ASVZ-80?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD6645ASVZ-80 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD6645ASVZ-80?
AD6645ASVZ-80 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD6645ASVZ-80 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD6645ASVZ-80?
For technical support, including AD6645ASVZ-80 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD6645ASVZ-80 requirements.
6.How does Aetrix verify that AD6645ASVZ-80 is sourced from the original manufacturer or authorized distributors?
All AD6645ASVZ-80 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD6645ASVZ-80 meets industry standards.
7.What is the process for return or replacement of AD6645ASVZ-80?
All AD6645ASVZ-80 units undergo pre-shipment inspection (PSI). If there is an issue with AD6645ASVZ-80, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD6645ASVZ-80 part is unused and in its original packaging.
Return procedure for AD6645ASVZ-80:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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