Analog Devices Inc. AD6659-80EBZ

Overview

AD6659-80EBZ from Analog Devices is a dual-channel, 12-bit, 80 MSPS intermediate frequency (IF) receiver evaluation board built around the AD6659 mixed-signal IC. It integrates two high-performance ADCs with noise shaping requantizer (NSR), quadrature error correction (QEC), and dc offset correction - enabling simultaneous main/diversity signal digitization for wireless infrastructure receivers. Key confirmed specs: 700 MHz analog input bandwidth, 81.5 dBFS SNR (16 MHz BW, NSR enabled), 90 dBc SFDR (up to 70 MHz), and 1.8 V analog supply.

For engineers reviewing the AD6659-80EBZ datasheet, AD6659-80EBZ pinout, AD6659-80EBZ application, or AD6659-80EBZ equivalent, this page delivers verified technical context, real-world IF receiver use cases, functional block-level design insights, and sourcing support for RF system prototyping - all grounded in the official AD6659 Rev. A datasheet and evaluation board documentation.

Technical Context

The AD6659-80EBZ implements a dual-pipelined ADC architecture with integrated digital signal conditioning: each channel features a 12-bit, 80 MSPS converter feeding an NSR block that reshapes quantization noise into a programmable 20% Nyquist band (e.g., 16 MHz at 80 MSPS), boosting SNR by up to 9.5 dB within that band. The board supports SPI-configurable QEC to correct inter-channel gain/phase mismatch and dc offset - critical for I/Q demodulation accuracy in direct-conversion receivers.

It provides differential clock inputs compatible with CMOS/LVDS/LVPECL, 2 V_p-p differential analog inputs with 700 MHz bandwidth, and CMOS digital outputs configurable for 1.8 V or 3.3 V logic levels. Timing includes programmable data-clock alignment, 9–11 cycle pipeline latency (depending on NSR/QEC enable state), and <0.1 ps rms aperture jitter - ensuring precise sampling for wideband IF signals up to 200 MHz.

Key Specifications

Availability

AD6659-80EBZ is available at Aetrix Electronics and suitable for RF prototyping, wireless infrastructure development, and software-defined radio (SDR) validation requiring stable component supply, traceable evaluation hardware, and documented performance benchmarks.

Supply support for AD6659-80EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, headquartered in Norwood, MA, with over 50 years of innovation in precision data conversion and RF solutions.

The AD6659-80EBZ belongs to Analog Devices' high-speed IF receiver product line, designed specifically for communications infrastructure applications demanding dual-channel synchronization, wide instantaneous bandwidth, and integrated digital correction - including LTE, W-CDMA, and TD-SCDMA base stations.

FAQ

What is the primary function of the AD6659-80EBZ evaluation board?

The AD6659-80EBZ is a fully populated evaluation platform for the AD6659 dual-channel IF receiver IC. Its primary function is to enable rapid characterization and integration of the AD6659's 12-bit, 80 MSPS ADCs with integrated NSR and QEC in real-world RF systems - supporting tasks like SNR/SFDR measurement, SPI register configuration, clock jitter analysis, and I/Q signal path validation. The AD6659-80EBZ includes reference clock distribution, analog input matching networks, and FPGA-compatible digital output headers.

Does the AD6659-80EBZ support both NSR-enabled and NSR-disabled operation modes?

Yes, the AD6659-80EBZ supports both NSR modes via SPI configuration. With NSR enabled, the AD6659-80EBZ achieves up to 81.5 dBFS SNR in a 16 MHz bandwidth centered within the Nyquist zone (e.g., 9.7 MHz input at 80 MSPS). With NSR disabled, it delivers 72 dBFS SNR across the full 0–40 MHz baseband or up to 70 MHz via undersampling - preserving 12-bit resolution while maximizing instantaneous bandwidth. This dual-mode capability is accessible through the board's onboard USB interface and Analog Devices' VisualAnalog software.

What clock input standards does the AD6659-80EBZ accept?

The AD6659-80EBZ accepts differential clock inputs compliant with CMOS, LVDS, or LVPECL standards via its CLK+/CLK− pins. The board includes on-board termination and biasing to support all three interfaces without hardware modification. Internal common-mode voltage is fixed at 0.9 V, and differential input voltage range spans 0.2 V_p-p to 3.6 V_p-p. An optional duty cycle stabilizer (DCS) can be enabled to maintain <6.25 ns pulse width tolerance even with highly asymmetric input clocks - a key feature validated on the AD6659-80EBZ during RF lab testing.

How is analog input interfaced on the AD6659-80EBZ?

The AD6659-80EBZ provides SMA connectors for differential analog inputs to both Channel A (VIN+A/VIN−A) and Channel B (VIN+B/VIN−B), each with 50 Ω impedance matching and DC-blocking capacitors. Inputs are optimized for 2 V_p-p differential swing and support common-mode voltage adjustment via the VCM pin. The board's analog section includes matched trace routing, dedicated AGND planes, and isolated AVDD decoupling - ensuring the specified 700 MHz input bandwidth and <0.1 ps rms jitter performance of the underlying AD6659 IC is preserved in evaluation use.

Can the AD6659-80EBZ be used for diversity reception in MIMO systems?

Yes, the AD6659-80EBZ is explicitly designed for diversity reception applications. Its dual synchronized ADC channels, sub-picosecond inter-channel timing alignment (<0.1 ns skew), and integrated QEC allow simultaneous digitization of main and diversity antenna paths with calibrated gain/phase matching - directly supporting smart antenna and MIMO baseband processing. The board's SYNC input enables deterministic multi-board synchronization, and the AD6659-80EBZ's documented 110 dB crosstalk rejection ensures minimal inter-channel interference during concurrent sampling.