Analog Devices Inc. AD6672-250EBZ

Overview

AD6672-250EBZ from Analog Devices is a high-speed analog-to-digital converter evaluation board designed for the AD6672 11-bit, 250 MSPS ADC. It supports JESD204B subclass 1 serial interface, operates with 2.5 V FPGA I/O voltage, and requires a clean 10–14 dBm analog clock input at J506 for full-rate sampling.

For engineers reviewing the AD6672-250EBZ datasheet, AD6672-250EBZ pinout, AD6672-250EBZ application, or AD6672-250EBZ equivalent, this board enables rapid validation of RF-sampling ADC performance in wideband receiver chains, LTE/5G infrastructure signal capture, and high-fidelity data acquisition systems using VisualAnalog and SPIController software tools.

Technical Context

The AD6672-250EBZ implements a complete test platform for the AD6672 ADC, interfacing directly with the HSC-ADC-EVALCZ FPGA-based capture board via high-density mezzanine connectors. It provides configurable analog input (J301, 50 Ω, single-ended), precision clock input (J506, 10–14 dBm), and on-board power regulation for core and I/O rails.

Signal integrity is maintained through shielded coaxial routing, narrow-band band-pass filtering support (e.g., TTE, Allen Avionics), and jumper-selectable FPGA I/O voltage (2.5 V via J9). The board relies on external 6 V/2 A switching supplies and requires SPI configuration (AD6672spiR03.cfg) and FPGA bitstream programming (AD9642_0.bin for XCPZ-branded boards) for operation.

Key Specifications

Availability

AD6672-250EBZ is available at Aetrix Electronics and suitable for RF receiver development, wireless infrastructure prototyping, and high-speed data acquisition systems requiring stable component supply and validated reference design integration.

Supply support for AD6672-250EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD6672-250EBZ belongs to Analog Devices' high-speed ADC evaluation platform family, engineered specifically to accelerate time-to-test for RF-sampling receivers in communications, defense, and instrumentation applications.

FAQ

What is the primary function of the AD6672-250EBZ?

The AD6672-250EBZ is an evaluation board for the AD6672 11-bit, 250 MSPS analog-to-digital converter. It provides a complete hardware and software environment-including analog input, clock interface, power conditioning, and JESD204B connectivity-to validate ADC performance in real-world RF sampling applications. The AD6672-250EBZ must be used with the HSC-ADC-EVALCZ capture board and VisualAnalog/SPIController software to operate.

Which software tools are required to operate the AD6672-250EBZ?

Operation of the AD6672-250EBZ requires VisualAnalog for FFT analysis and data visualization, and SPIController for register-level configuration of the AD6672 device. Configuration files AD6672spiR03.cfg and FPGA bitstream AD9642_0.bin (for XCPZ-branded boards) are mandatory. All tools and documentation are hosted at analog.com/fifo.

What clock signal specifications are required at J506 for the AD6672-250EBZ?

The AD6672-250EBZ requires a low-jitter analog clock input at connector J506 with a level between 10 dBm and 14 dBm. This drives the AD6672's sampling core at its rated 250 MSPS. If the internal clock divider is enabled, the input frequency must be scaled accordingly-e.g., 500 MHz for ÷2 mode-while maintaining the same power level specification.

How is analog input signal integrity maintained on the AD6672-250EBZ?

Analog input integrity on the AD6672-250EBZ is maintained using a 50 Ω single-ended path via connector J301, supported by shielded RG-58 coaxial cabling and optional narrow-band band-pass filtering (e.g., TTE or K&L filters). Signal generator output should be set to 8–12 dBm to achieve near-full-scale ADC input without clipping or distortion.

Can the AD6672-250EBZ operate independently without the HSC-ADC-EVALCZ board?

No-the AD6672-250EBZ is not a standalone system. It is a mezzanine evaluation board that must be mated with the HSC-ADC-EVALCZ FPGA-based data capture board to provide JESD204B serialization, FIFO buffering, USB 2.0 host interface, and FPGA-controlled ADC configuration. Without the HSC-ADC-EVALCZ, the AD6672-250EBZ cannot acquire or transfer sampled data to a PC.