Analog Devices Inc. AD6674-1000EBZ

Overview

AD6674-1000EBZ from Analog Devices is a 385 MHz bandwidth, dual-channel, 14-bit, 1.0 GSPS intermediate frequency (IF) diversity receiver evaluation board. It integrates two high-speed ADCs, four wideband digital downconverters (DDCs), noise shaping requantizer (NSR), and variable dynamic range (VDR) processing blocks. Designed for multiband 4G/LTE-A base station receivers and DOCSIS 3.0 CMTS upstream paths, it supports JESD204B Subclass 1 serial output at up to 12.5 Gbps per lane.

For engineers reviewing the AD6674-1000EBZ datasheet, AD6674-1000EBZ pinout, AD6674-1000EBZ application, or AD6674-1000EBZ equivalent, key selection criteria include its 1.0 GSPS sampling rate, 385 MHz IF bandwidth, 95 dB channel isolation, −153 dBFS/Hz noise density, and support for programmable NSR/VDR modes in communications infrastructure signal chains.

Technical Context

The AD6674-1000EBZ implements two independent 14-bit pipelined ADC cores with differential buffered inputs, each feeding four cascaded DDC stages: a 12-bit NCO, up to four half-band decimation filters, and configurable gain/complex-to-real conversion. The board enables full evaluation of the underlying AD6674-1000 IC's dual-channel architecture, including simultaneous NSR (21%/28% BW modes) and VDR operation for digital predistortion monitoring.

Digital outputs conform to JESD204B Subclass 1 with flexible lane configuration (2- or 4-lane), SYSREF±-based multidevice synchronization, and SPI-controlled fast detect (FD_A/FD_B) with 28-cycle latency. Clock input accepts LVDS/LVPECL at up to 4 GHz, internally divided by 1/2/4/8 to support the 1.0 GSPS sample rate.

Key Specifications

Availability

AD6674-1000EBZ is available at Aetrix Electronics and suitable for 4G/LTE-A base station development, DOCSIS 3.0 CMTS upstream receiver validation, and HFC reverse-path receiver prototyping requiring stable component supply and full-feature evaluation capability.

Supply support for AD6674-1000EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD6674 product line delivers integrated IF receiver solutions for communications infrastructure, combining high-speed ADCs with on-chip DDC, NSR, and VDR processing to reduce FPGA resource load and simplify wideband receiver design.

FAQ

What is the AD6674-1000EBZ used for?

The AD6674-1000EBZ is an evaluation board for the AD6674-1000 dual-channel IF receiver IC. It enables full characterization of the device's 1.0 GSPS sampling, 385 MHz bandwidth, JESD204B Subclass 1 output, NSR, and VDR features in real-world 4G/LTE-A and DOCSIS 3.0 receiver applications. Engineers use AD6674-1000EBZ to validate signal chain performance before system integration.

Does the AD6674-1000EBZ support JESD204B Subclass 1 synchronization?

Yes, the AD6674-1000EBZ fully supports JESD204B Subclass 1 operation, including deterministic latency, SYSREF±-based multidevice alignment, and SYNCINB± input for link initialization. The board routes all required timing signals-including SYSREF±, SYNCINB±, and differential clocks-to enable precise synchronization in multi-board or multi-IC systems using AD6674-1000EBZ.

What are the power supply requirements for the AD6674-1000EBZ?

The AD6674-1000EBZ requires five regulated supplies: 1.25 V (AVDD1, AVDD1_SR, DVDD, DRVDD), 2.5 V (AVDD2), 3.3 V (AVDD3), and 1.7–3.4 V (SPIVDD). Total typical power consumption is 3.6 W at 1.0 GSPS. The board includes on-board LDOs and power sequencing circuitry to meet the strict AVDD/DVDD ramp requirements specified for the AD6674-1000 IC.

Can the AD6674-1000EBZ be used to evaluate NSR and VDR modes simultaneously?

Yes, the AD6674-1000EBZ supports concurrent evaluation of NSR and VDR modes via SPI configuration. Each ADC channel can independently enable NSR (for enhanced SNR in reduced bandwidth) and VDR (for dynamic range optimization in DPD observation paths). The board's firmware and GUI allow real-time switching and parameter tuning of both features on AD6674-1000EBZ during live signal capture.

What clock sources are compatible with the AD6674-1000EBZ?

The AD6674-1000EBZ accepts differential LVDS or LVPECL clock inputs at frequencies up to 4 GHz on its CLK+/CLK− pins. An on-board clock divider (÷1/÷2/÷4/÷8) allows flexible generation of the 1.0 GHz sampling clock from common synthesizers. The board also supports external SYSREF± and SYNCINB± inputs for JESD204B link synchronization when using AD6674-1000EBZ in multi-device configurations.