Analog Devices Inc. AD6674-750EBZ

Overview

AD6674-750EBZ from Analog Devices is a 385 MHz bandwidth, dual-channel, 14-bit, 750 MSPS intermediate frequency (IF) diversity receiver evaluation board. It integrates two high-speed ADCs with on-chip digital downconverters (DDCs), noise shaping requantizer (NSR), and variable dynamic range (VDR) processing blocks. Designed for multiband wireless infrastructure, it delivers 66.7 dBFS SNR at 340 MHz input and supports JESD204B Subclass 1 serial output for FPGA interfacing in LTE-A and DOCSIS 3.0 upstream receivers.

For engineers reviewing the AD6674-750EBZ datasheet, AD6674-750EBZ pinout, AD6674-750EBZ application, or AD6674-750EBZ equivalent, this evaluation board enables rapid validation of wideband IF sampling, AGC implementation via fast detect outputs (FD_A/FD_B), DDC configuration (NCO + up to 4 half-band filters), NSR-enhanced SNR in narrow subbands, and VDR-based digital predistortion monitoring - all within a single 9 mm × 9 mm LFCSP package platform.

Technical Context

The AD6674-750EBZ implements two independent 14-bit pipelined ADC cores operating at 750 MSPS, each feeding four cascaded DDC signal chains: a 12-bit NCO, up to four half-band decimation filters, NSR, and VDR blocks. Input support spans 1.46–1.94 V_p-p differential with buffered analog inputs optimized for 2 GHz full-power bandwidth and low-latency fast detect (28 clock cycles).

Digital output uses JESD204B Subclass 1 with configurable 2- or 4-lane CML serialization (up to 7.5 Gbps/lane), synchronized via SYSREF± and SYNCINB±. Power management includes standby (1.4 W) and power-down (835 mW) modes, while SPI control (1.8–3.4 V compatible) configures all signal processing features, including real/complex IF mode selection and mask-based VDR thresholding.

Key Specifications

Availability

AD6674-750EBZ is available at Aetrix Electronics and suitable for LTE-A base station development, DOCSIS 3.0 CMTS upstream path validation, and HFC reverse-path receiver prototyping requiring stable component supply and full evaluation board traceability.

Supply support for AD6674-750EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, serving communications, industrial, and aerospace markets since 1965.

The AD6674 product line targets wideband IF sampling in multiband, multimode digital receivers - specifically engineered to replace discrete ADC + FPGA signal processing pipelines with integrated DDC, NSR, and VDR functionality in compact LFCSP packages.

FAQ

What is the AD6674-750EBZ used for?

The AD6674-750EBZ is an evaluation board for the AD6674-750 dual-channel IF receiver IC. It enables hardware validation of 750 MSPS sampling, JESD204B Subclass 1 interface timing, DDC configuration (NCO + half-band filters), NSR-enhanced SNR, and VDR-based digital predistortion monitoring. Engineers use the AD6674-750EBZ to verify system-level performance before integrating the AD6674-750 into final RF front-end designs for LTE-A and cable infrastructure.

Does the AD6674-750EBZ support both real and complex IF sampling?

Yes, the AD6674-750EBZ supports both real IF and complex IF (I/Q) sampling through its onboard AD6674-750 IC. The device's DDC architecture allows programmable selection of I/Q input sources and complex-to-real conversion modes via SPI registers. This flexibility makes the AD6674-750EBZ suitable for zero-IF, complex IF, and real IF receive architectures common in modern wireless infrastructure.

What are the key power supply requirements for the AD6674-750EBZ?

The AD6674-750EBZ requires six regulated supplies: AVDD1 (1.25 V), AVDD2 (2.5 V), AVDD3 (3.3 V), AVDD1_SR (1.25 V), DVDD (1.25 V), DRVDD (1.25 V), and SPIVDD (1.8–3.4 V). These match the AD6674-750 IC's internal rail architecture and must meet tight tolerance specs (±30 mV) to ensure specified SNR and SFDR performance. The board includes dedicated LDOs and filtering per supply domain.

How does the fast detect feature work on the AD6674-750EBZ?

The AD6674-750EBZ exposes FD_A and FD_B CMOS outputs from the AD6674-750 IC, providing low-latency (28 clock cycles) overrange indication for each ADC channel. Thresholds are programmable via SPI register 0x245. When input exceeds the set level, the corresponding FD pin asserts high, enabling rapid AGC loop response - critical for protecting downstream FPGAs and maintaining signal integrity in burst-mode systems like TD-SCDMA.

Can the AD6674-750EBZ be synchronized with other JESD204B devices?

Yes, the AD6674-750EBZ supports multidevice synchronization using SYSREF± and SYNCINB± differential inputs. These pins align the internal DDC NCO phase, serializer framing, and lane alignment across multiple AD6674-750EBZ boards or with companion DACs/FPGAs. Synchronization is essential for coherent MIMO and phased-array receiver calibration - a core capability validated on the AD6674-750EBZ.