Analog Devices Inc. AD6674-LF750EBZ

Overview

AD6674-LF750EBZ from Analog Devices is a low-frequency evaluation board designed for the AD6674-750 dual-channel, 14-bit, 750 MSPS RF-sampling analog-to-digital converter. It supports up to 1 GHz input bandwidth, JESD204B interface (4 lanes, 7.5 Gbps), and real/complex signal processing modes including NSR and VDR. Used for IF diversity receiver validation in wireless infrastructure and radar systems.

For engineers reviewing the AD6674-LF750EBZ datasheet, AD6674-LF750EBZ pinout, AD6674-LF750EBZ application, or AD6674-LF750EBZ equivalent, this page delivers verified hardware configuration steps, SPI register mapping, FPGA capture integration (ADS7-V1/V2), clocking requirements (750 MHz sample clock, 187.5/375 MHz REFCLK), and mode-specific setup for NSR, VDR, and DDC-based decimation.

Technical Context

The AD6674-LF750EBZ implements a full-bandwidth-capable analog front-end with wideband balun-driven inputs (P200/P202), on-board LDOs, and FMC-compliant power delivery (12 V/1 A and 3.3 V/3 A from host capture board). It interfaces exclusively with ADS7-V1EBZ or ADS7-V2EBZ FPGA data capture kits via high-density FMC connector.

Board revision 9680CE02B supports two distinct ADC operating modes: Noise Shaped Requantizer (NSR) with 21% bandwidth and ~3 dB signal loss, and Variable Dynamic Range (VDR) with 25% complex bandwidth and zero signal attenuation. Both modes use JESD204B subclass 1, lane rate configurable via register 0x56E, and PLL lock detection at 0x56F.

Key Specifications

Availability

AD6674-LF750EBZ is available at Aetrix Electronics and suitable for wireless infrastructure prototyping, radar IF receiver development, and 5G massive MIMO baseband validation requiring stable component supply and full documentation traceability.

Supply support for AD6674-LF750EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD6674 evaluation board series supports the AD6674 family of high-speed RF-sampling ADCs engineered for demanding communications and defense applications requiring wide instantaneous bandwidth, flexible digital processing, and deterministic JESD204B data transport.

FAQ

What is the primary function of the AD6674-LF750EBZ evaluation board?

The AD6674-LF750EBZ is a dedicated low-frequency evaluation platform for the AD6674-750 RF-sampling ADC. It enables hardware validation of key features including NSR and VDR modes, dual-DDC operation, JESD204B link configuration, and real/complex signal processing - all within a 1 GHz input bandwidth envelope. Unlike full-bandwidth boards, it optimizes analog path performance for lower-frequency IF applications while retaining full register-level control of the AD6674-750 device.

Which FPGA data capture boards are compatible with AD6674-LF750EBZ?

The AD6674-LF750EBZ is validated exclusively with the ADS7-V1EBZ and ADS7-V2EBZ FPGA-based data capture kits. These boards provide the required JESD204B subclass 1 link layer, programmable bin files (ad9680_ads7v1.bin/ad9680_ads7v2.bin), and ACE/VisualAnalog software integration. No other capture platforms - including ADS7-V3 or third-party FMC carriers - are supported per Analog Devices' official documentation and board revision 9680CE02B design constraints.

What clock frequencies must be applied to AD6674-LF750EBZ for NSR and VDR operation?

For NSR mode, AD6674-LF750EBZ requires a 750 MHz sample clock at J801 and a 187.5 MHz REFCLK at J804. For VDR mode, it requires the same 750 MHz sample clock but a 375 MHz REFCLK. These values derive directly from the AD6674-750's internal PLL and JESD204B lane rate calculation (L=4, M=2, F=1, N′=16), and mismatched REFCLK frequencies will prevent PLL lock (register 0x56F ≠ 0x80) and JESD link initialization.

Does AD6674-LF750EBZ support standalone operation without an FPGA capture board?

No. The AD6674-LF750EBZ has no onboard data storage, USB interface, or Ethernet connectivity. It relies entirely on an ADS7-V1EBZ or ADS7-V2EBZ FPGA capture board for power (12 V/1 A and 3.3 V/3 A via FMC), JESD204B serialization, real-time data streaming, and SPI register access. All configuration, data capture, and analysis - including ACE plugin operation and VisualAnalog FFT generation - require the paired FPGA kit.

How does AD6674-LF750EBZ differ from AD6674-750EBZ?

The AD6674-LF750EBZ uses board revision 9680CE02B and features optimized analog front-end components (baluns, filters, termination networks) for stable operation up to 1 GHz input bandwidth, whereas the AD6674-750EBZ (revision 9680CE04B) supports full 2 GHz bandwidth. Both target the AD6674-750, share identical SPI register maps and software interfaces (ACE/VisualAnalog), and require the same ADS7-V1/V2 capture boards - but LF variant prioritizes phase linearity and SNR below 1 GHz over ultra-wideband coverage.