Analog Devices Inc. AD671SD-750
- Part No.:
- AD671SD-750
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 24-CDIP (0.300", 7.62mm)
- Datasheet:
-
AD671SD-750.pdf
- Description:
- 12-BIT FLASH ADC
- Quantity:
- Payment:

- Shipping:

Inventory:209
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Product details
Overview
AD671SD-750 from Analog Devices is a monolithic 12-bit analog-to-digital converter with subranging flash architecture, 750 ns max conversion time, ±2.5 LSB integral nonlinearity over –55°C to +125°C, unipolar/bipolar input range selection via BPO/UPO pin, and OUT OF RANGE (OTR) flag output. It serves as a high-speed data acquisition front-end in military-grade instrumentation and radar signal processing systems.
For engineers reviewing the AD671SD-750 datasheet, AD671SD-750 pinout, AD671SD-750 application, or AD671SD-750 equivalent, this page delivers verified technical context, exact pin functions, real-world timing constraints, calibrated input range configurations, and validated alternatives for ruggedized embedded ADC selection.
Technical Context
The AD671SD-750 implements a four-stage subranging flash architecture: first two stages use 3-bit flash converters with DAC-based residue generation and overlap logic for error correction; third stage uses gain-of-four differential amplifier feeding coarse/fine 4-bit+4-bit ladder-matrix flash; final stage latches 12-bit output with OTR flag. All internal timing is generated on-chip from a single ENCODE rising edge.
Input range configuration is determined by strapping BPO/UPO (Pin 21) to AIN (0 V to +5 V), ACOM (0 V to +10 V), or REF IN (–5 V to +5 V); reference input requires external +5 V source (e.g., AD586) with 6.8 µF bulk capacitance; analog and digital grounds (ACOM/DCOM) are physically separated and joined only at the device.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - delivers 4096 discrete digital codes across full-scale input range |
| Conversion Time | 725–750 ns - defines minimum sampling interval of 1.33 MSps in continuous mode |
| Integral Nonlinearity | ±2.5 LSB (S grade) - limits end-point accuracy error to ±0.06% FSR at temperature extremes |
| Input Ranges | 0 V to +5 V, 0 V to +10 V, or –5 V to +5 V - selected by external pin strapping, no register programming required |
| Power Consumption | 475 mW typical - enables high-speed operation without forced-air cooling in sealed enclosures |
| Supply Voltages | +5 V (VCC/VLOGIC), –5 V (VEE) - dual-rail analog supply supports true bipolar input handling |
| Output Data Format | Offset binary or twos complement - selectable via MSB (Pin 13) inversion for direct DSP interface |
Pinout & Package
AD671SD-750 is housed in a 24-pin ceramic DIP (D-24A), 0.300 inch wide, MIL-STD-883 compliant, rated for –55°C to +125°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (BIT12) | Digital Output (LSB) | Least significant bit of 12-bit parallel output bus; must be terminated to avoid reflections at >1 MHz data rates |
| 12 (BIT1) | Digital Output (MSB) | Most significant bit; used with Pin 13 (MSB) to select offset binary vs. twos complement format |
| 13 (MSB) | Digital Output (Inverted MSB) | Provides twos complement output when enabled; tied high/low to configure data polarity |
| 14 (OTR) | Digital Output (Active-High Flag) | Asserts HIGH when input exceeds configured span; enables immediate fault detection without software polling |
| 15 (DAV) | Digital Output (Strobe) | Rising edge marks end-of-conversion; falling edge latches prior sample - supports pipelined data capture |
| 16 (ENCODE) | Digital Input (Edge-Triggered) | Rising edge initiates conversion; pulse width ≤50 ns ensures noise immunity during critical residue amplification phase |
| 19 (REF IN) | Analog Input (Reference) | Accepts external +5 V reference; requires 6.8 µF low-ESR capacitor to suppress DAC-induced current transients |
| 20 (AIN) | Analog Input (Signal) | High-dynamic-load node; source must settle within 12-bit accuracy (<1.22 mV @ 10 V) within 200 ns after ENCODE |
| 21 (BPO/UPO) | Analog Input (Mode Select) | Strap to AIN/ACOM/REF IN to configure 0–5 V / 0–10 V / ±5 V input range - no external resistors needed |
| 22 (ACOM) | Power (Analog Ground) | Low-impedance return for analog currents; joined to DCOM only at device to prevent ground-loop coupling |
| 23 (VCC) | Power (+5 V Analog) | Supplies high-speed bipolar circuitry; decoupled with 0.1 µF ceramic + 10 µF tantalum per Analog Devices layout guide |
| 24 (VEE) | Power (–5 V Analog) | Completes dual-rail analog supply; carries majority of input/reference current to minimize ACOM voltage drop |
Key Features
| Feature | Design Value |
|---|---|
| On-chip timing generator | Eliminates external clock distribution network; guarantees inter-flash settling time for residue amplifier |
| Digital error correction logic | Compensates for first-stage flash quantization errors using laser-trimmed thin-film resistor ladder |
| Separate analog/digital grounds (ACOM/DCOM) | Reduces code-dependent ground bounce; enables >70 dB SNR in mixed-signal PCB layouts without ground planes |
| Out-of-range (OTR) flag | Hardware-level overrange detection with <75 ns latency - replaces software clipping checks in real-time control loops |
| MIL-STD-883 screening option | Available in S-grade ceramic DIP with burn-in, hermetic seal, and radiation-hardened process for aerospace deployment |
Applications
| Radar Pulse Digitization | Military Data Acquisition |
|---|---|
Use Scenario: Capturing fast-rise RF envelope signals from pulse-Doppler radar receivers operating at 1–2 MSps. IC Role / Device Role / Timing Role: Front-end ADC converting conditioned IF outputs into 12-bit parallel words synchronized to system ENCODE strobe. Use Value: 750 ns conversion time enables full Nyquist sampling of 500 kHz baseband signals; OTR flag triggers immediate gain adjustment before saturation. | Use Scenario: High-reliability telemetry systems in guided munitions requiring operation from –55°C to +125°C. IC Role / Device Role / Timing Role: Ruggedized ADC interfacing with sensor signal chains under shock/vibration; powered from isolated ±5 V rails. Use Value: Ceramic DIP package and MIL-STD-883 compliance ensure mechanical stability; separate ACOM/DCOM prevents noise coupling in compact form factors. |
| Electronic Warfare Receivers | Avionics Signal Monitoring |
Use Scenario: Wideband intercept receivers digitizing 0–10 V IF outputs from channelized front-ends in ECM pods. IC Role / Device Role / Timing Role: High-speed ADC with programmable input span (via BPO/UPO strapping) adapting to varying signal levels across frequency bands. Use Value: Pin-strapped 0–10 V range eliminates need for external gain-switching circuitry; 1.5 kΩ input resistance minimizes loading on preceding filter stages. | Use Scenario: Engine health monitoring systems capturing analog outputs from pressure, temperature, and vibration sensors. IC Role / Device Role / Timing Role: Precision ADC acquiring slow-varying DC-coupled sensor signals with built-in bipolar (±5 V) support for differential transducers. Use Value: Bipolar input mode allows direct connection to bridge-based strain gauges; ±2.5 LSB INL ensures <0.1% measurement uncertainty over full temperature range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed 12-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD670SD-750 | 10-bit resolution, same 750 ns conversion time, identical pinout and package, lower power (350 mW) | Limited to applications requiring ≤10-bit precision; lacks OTR flag and bipolar zero calibration support | Select when system SNR budget permits 10-bit resolution and reduced thermal load is critical |
| HS-ADC12100S | 12-bit, 100 MSPS, CMOS process, 3.3 V digital I/O, serial LVDS output (not parallel) | Requires FPGA-based deserialization; incompatible pinout and power scheme; no native ±5 V analog interface | Choose for ultra-high-throughput systems where board space and serialization justify redesign |
Compared with AD671SD-750, AD670SD-750 trades resolution for lower power and cost in less demanding measurement roles, while HS-ADC12100S offers vastly higher speed at the expense of parallel interface simplicity, analog supply compatibility, and legacy system integration effort.
Availability
AD671SD-750 is available at Aetrix Electronics and suitable for radar pulse digitization, military data acquisition, electronic warfare receivers, and avionics signal monitoring requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AD671SD-750 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.
The AD671 product line was designed for high-speed, high-accuracy data acquisition in defense, aerospace, and industrial test equipment where monolithic reliability, MIL-grade temperature operation, and deterministic conversion timing are mandatory.
FAQ
What is the guaranteed operating temperature range for AD671SD-750?
The AD671SD-750 is specified for continuous operation from –55°C to +125°C. This S-grade rating is validated per MIL-STD-883 test conditions and applies to both electrical performance (e.g., ±2.5 LSB INL) and timing parameters (e.g., 750 ns max conversion time) across the full range. The ceramic DIP package provides mechanical stability under thermal cycling stress encountered in aerospace deployments.
How does the BPO/UPO pin configure input ranges on AD671SD-750?
The BPO/UPO pin (Pin 21) selects AD671SD-750 input range via hardwired strapping: connect to AIN for 0 V to +5 V span, to ACOM for 0 V to +10 V span, or to REF IN for –5 V to +5 V bipolar span. No external components or registers are needed. This passive configuration avoids firmware dependencies and ensures deterministic behavior at power-up.
What is the function of the MSB pin (Pin 13) on AD671SD-750?
The MSB pin (Pin 13) on AD671SD-750 provides an inverted version of BIT1 (Pin 12) to enable twos complement output format. When MSB is used, the 12-bit word represents signed values (–2048 to +2047); when unused, standard offset binary format (0 to 4095) is delivered. This hardware-selectable format simplifies interface to DSPs or FPGAs requiring signed arithmetic.
Can AD671SD-750 operate with a single +5 V supply?
No, AD671SD-750 requires three independent supplies: +5 V on VCC (Pin 23), –5 V on VEE (Pin 24), and +5 V on VLOGIC (Pin 17). The dual-rail analog supply (±5 V) is essential for bipolar input operation and internal DAC linearity. Using a single +5 V rail would violate absolute maximum ratings and prevent proper functioning of the residue amplifier and flash comparators.
What external components are mandatory for stable AD671SD-750 operation?
Mandatory external components for AD671SD-750 include: (1) 6.8 µF low-ESR capacitor between REF IN (Pin 19) and ACOM (Pin 22); (2) 0.1 µF ceramic + 10 µF tantalum decoupling capacitors on VCC (Pin 23) and VEE (Pin 24); (3) proper grounding - ACOM and DCOM joined only at the AD671SD-750 package. Omission of the REF IN capacitor causes reference droop and gain error exceeding ±0.25% FSR.
AD671SD-750 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- AD671
- Package/Case:
- 24-CDIP (0.300", 7.62mm)
- Packaging:
- Bulk
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- -
- Architecture:
- Flash
- Reference Type:
- External
- Voltage - Supply, Analog:
- 4.75V ~ 5.25V
- Voltage - Supply, Digital:
- 4.75V ~ 5.25V
- Features:
- -
- Operating Temperature:
- -55°C ~ 125°C
- Supplier Device Package:
- 24-CDIP
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
AD671SD-750 FAQ
1.How can I place an order for AD671SD-750 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD671SD-750 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD671SD-750 reliable?
The price and inventory of AD671SD-750 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD671SD-750 is usually 5 days.
3.What payment methods are accepted for AD671SD-750?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD671SD-750 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD671SD-750?
AD671SD-750 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD671SD-750 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD671SD-750?
For technical support, including AD671SD-750 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD671SD-750 requirements.
6.How does Aetrix verify that AD671SD-750 is sourced from the original manufacturer or authorized distributors?
All AD671SD-750 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD671SD-750 meets industry standards.
7.What is the process for return or replacement of AD671SD-750?
All AD671SD-750 units undergo pre-shipment inspection (PSI). If there is an issue with AD671SD-750, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD671SD-750 part is unused and in its original packaging.
Return procedure for AD671SD-750:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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