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Analog Devices Inc. AD673JN
- Part No.:
- AD673JN
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
AD673JN.pdf
- Description:
- IC ADC 8BIT W/REF/CLK/COMP 20DIP
- Quantity:
- Payment:
- Shipping:
Inventory:1,381
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Product details
Overview
AD673JN from Analog Devices is a complete 8-bit successive approximation analog-to-digital converter (ADC) with integrated buried Zener reference, on-chip clock, comparator, SAR register, and 3-state digital outputs. It delivers ±1/2 LSB relative accuracy, supports unipolar (0 V to +10 V) and bipolar (–5 V to +5 V) input ranges, and achieves full conversion in ≤20 µs using +5 V and –12 V to –15 V supplies - enabling self-contained data acquisition in industrial sensor interfaces and test equipment.
For engineers reviewing the AD673JN datasheet, AD673JN pinout, AD673JN application, or AD673JN equivalent, this page provides verified technical context, exact pin functions, real-world interface timing constraints, calibrated input range configuration methods, and validated alternatives for legacy system replacement or MIL-qualified redesign.
Technical Context
The AD673JN implements successive approximation via integrated injection logic (I2L) SAR architecture, with an internal 8-bit current-output DAC matched to a laser-trimmed 5 kΩ thin-film input resistor. Its temperature-compensated buried Zener reference ensures ±1 LSB stability over 0°C to +70°C, and its dual common (analog/digital) design permits up to ±200 mV ground offset without performance degradation.
Conversion is initiated by the trailing edge of a ≥500 ns CONVERT pulse; DATA READY (DR) asserts within 1.5 µs after the leading edge to signal reset completion, then deasserts upon conversion finish. Data output buffers are enabled via DATA ENABLE (DE), supporting microprocessor bus interfacing without external latches or glue logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 8 bits - guarantees monotonic transfer function with no missing codes across full operating temperature range. |
| Relative Accuracy | ±1/2 LSB max - ensures code transition points deviate < ±19.5 mV from ideal line under unipolar 0–10 V full-scale. |
| Conversion Time | 10–30 µs - enables sampling rates up to 100 kSPS in burst mode; typical 20 µs allows tight synchronization with microprocessor RD/WR cycles. |
| Analog Input Ranges | Unipolar: 0 V to +10 V; Bipolar: –5 V to +5 V - selected by grounding (unipolar) or floating (bipolar) Pin 16, no external components required. |
| Supply Voltages | +5 V (±0.5 V) and –12 V to –15 V - negative rail tolerance supports stable operation with aging or load-varied power supplies. |
| Output Interface | 8-bit 3-state TTL-compatible outputs (DB0–DB7) with 3.2 mA sink / 0.5 mA source drive - directly connects to 8080/8085/Z80 data buses without level-shifting. |
| Reference Stability | Buried Zener with laser-trimmed SiCr resistor ladder - maintains ±1/2 LSB accuracy from 0°C to +70°C without external calibration. |
Pinout & Package
AD673JN is supplied in a 20-pin plastic DIP (N-20) package with 0.300-inch wide body, through-hole mounting, and industry-standard footprint compatible with socketed prototyping and production PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIN 1 (NC) | Internal test point | Must be left floating; not connected to any internal circuitry per manufacturer specification. |
| PIN 2 (NC) | Internal test point | Must be left floating; no functional connection or electrical role in normal operation. |
| PIN 3 (DIGITAL COMMON) | Digital ground reference | Return path for all logic inputs/outputs; must be isolated from analog common except at single-point system ground. |
| PIN 4 (DATA READY) | Conversion status flag | Active-low open-collector output; goes low ≤30 µs after CONVERT falling edge to signal valid data availability. |
| PIN 5 (NC) | No connect | Not bonded internally; electrically inert and must remain unconnected. |
| PIN 6 (DATA ENABLE) | Output buffer control | Active-high TTL input; enables DB0–DB7 drivers when high; must be held high during conversion to avoid bus contention. |
| PIN 7 (NC) | No connect | Not bonded internally; electrically inert and must remain unconnected. |
| PIN 8 (LSB DB0) | Data output bit 0 | Least significant bit of conversion result; driven low/high or placed in high-impedance state per DATA ENABLE control. |
| PIN 9 (DB1) | Data output bit 1 | Second LSB; synchronized with DR and DE timing; requires ≤250 ns access time for reliable microprocessor read. |
| PIN 10 (ANALOG IN) | Analog signal input | Current-input node referenced to ANALOG COMMON; accepts 0–10 V (unipolar) or –5–+5 V (bipolar) via 5 kΩ internal resistor. |
| PIN 11 (ANALOG COMMON) | Analog ground reference | Return for analog input and internal DAC; carries up to 2 mA transient current during conversion; must be decoupled separately from DIGITAL COMMON. |
| PIN 12 (BIPOLAR OFFSET) | Input range selection | Open = bipolar (–5 V to +5 V); grounded to DIGITAL COMMON = unipolar (0 V to +10 V); controls internal offset current injection. |
| PIN 13 (DB2) | Data output bit 2 | Third LSB; part of 8-bit parallel bus interface; shares timing and loading characteristics with DB0–DB7. |
| PIN 14 (DB3) | Data output bit 3 | Fourth LSB; designed for direct connection to 8-bit microprocessor data bus without buffering. |
| PIN 15 (DB4) | Data output bit 4 | Fifth LSB; operates at TTL voltage levels (0.4 V low / 2.4 V high) with guaranteed 3.2 mA sink capability. |
| PIN 16 (DB5) | Data output bit 5 | Sixth LSB; electrically identical to other DBx pins; timing-critical for synchronous read operations. |
| PIN 17 (DB6) | Data output bit 6 | Seventh LSB; shares same output leakage (<640 µA) and source/sink specs as full bus. |
| PIN 18 (MSB DB7) | Data output bit 7 | Most significant bit; defines sign in bipolar mode (1 = positive); critical for zero-crossing detection in differential measurements. |
| PIN 19 (V+) | Positive supply | +5 V supply pin; must be bypassed with 0.1 µF ceramic capacitor to DIGITAL COMMON near the package. |
| PIN 20 (CONVERT) | Conversion trigger | Positive-edge sensitive input; ≥500 ns pulse width required; falling edge initiates SAR cycle; TTL-compatible with 2.0 V min "1" threshold. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Zener reference | Eliminates need for external precision voltage reference or trimming resistors - reduces BOM count and layout area in compact DAQ modules. |
| Configurable unipolar/bipolar input | Single-pin (Pin 16) selection enables dual-range support without hardware change - simplifies test fixture design for multi-signal calibration systems. |
| No missing codes over temperature | Guaranteed monotonicity from 0°C to +70°C ensures error-free position sensing or closed-loop control where code reversals cause instability. |
| Self-contained conversion timing | On-chip clock and SAR eliminate external timing generators - enables deterministic 20 µs conversion independent of processor clock jitter. |
| Separate analog/digital commons | Allows localized ground separation to suppress digital switching noise from corrupting analog input integrity - critical for <0.1% THD measurements. |
Applications
| Industrial Process Monitoring | Automated Test Equipment (ATE) |
|---|---|
|
Use Scenario: Continuous voltage monitoring of 4–20 mA loop transmitters via precision shunt resistor in PLC backplane modules. IC Role / Device Role / Timing Role: ADC front-end converting conditioned analog signals into 8-bit digital words synchronized to scan cycle timer. Use Value: ±1/2 LSB accuracy ensures <0.2% full-scale measurement fidelity across ambient temperature swings in factory-floor cabinets. |
Use Scenario: Digitizing stimulus response waveforms during semiconductor parametric testing on benchtop ATE platforms. IC Role / Device Role / Timing Role: High-reliability sampling node triggered by pattern generator's CONVERT pulse with sub-µs timing predictability. Use Value: 20 µs conversion time enables 50 kSPS burst capture of transient faults without FIFO buffering or external memory. |
| Legacy Avionics Data Acquisition | Military Ground Support Equipment |
|
Use Scenario: Retrofitting analog sensor channels (temperature, pressure) in aging aircraft maintenance diagnostic units with obsolescence-resistant components. IC Role / Device Role / Timing Role: Drop-in replacement for discontinued 8-bit ADCs requiring identical pinout, supply rails, and timing behavior. Use Value: Plastic DIP package and 0°C to +70°C rating match original equipment form-fit-function while maintaining MIL-STD-883 traceability path via AD673SD2. |
Use Scenario: Field-deployable battery-powered environmental monitors logging vibration, humidity, and voltage in tactical comms shelters. IC Role / Device Role / Timing Role: Low-power analog front-end digitizing conditioned sensor outputs under intermittent CPU control. Use Value: Dual-supply operation (+5 V / –12 V) enables direct interface with legacy op-amp signal chains without level-shifting circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit successive approximation ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7572A | Successive approximation architecture with internal reference; 12-bit resolution; 25 µs conversion time; +5 V only supply (no negative rail required). | Higher resolution but slower and incompatible supply scheme - unsuitable for bipolar input or –12 V legacy systems. | Select AD7572A only if upgrading resolution is prioritized and system can accommodate single-supply operation and longer conversion latency. |
| MAX160 | CMOS 8-bit SAR ADC; +5 V supply only; 10 µs conversion; no internal reference - requires external 2.5 V reference and input scaling resistors. | Lacks integrated reference and bipolar capability - increases component count and calibration complexity for unipolar/bipolar flexibility. | Choose MAX160 only for cost-sensitive, space-constrained designs where external reference and scaling are already present and bipolar mode is unnecessary. |
Compared with AD673JN, AD7572A offers higher resolution but eliminates bipolar input support and requires redesign of power delivery, while MAX160 reduces integration level and adds calibration overhead - making AD673JN uniquely suited for drop-in replacement in legacy dual-supply, range-flexible systems.
Availability
AD673JN is available at Aetrix Electronics and suitable for industrial process monitoring, automated test equipment, legacy avionics retrofit, military ground support equipment, and precision sensor interface applications requiring stable component supply across extended product lifecycles.
Supply support for AD673JN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.
The AD673 belongs to Analog Devices' legacy precision data acquisition IC family, engineered specifically for embedded instrumentation, industrial control, and defense systems requiring guaranteed monotonicity, dual-supply compatibility, and long-term reliability without recalibration.
FAQ
What is the maximum conversion rate supported by the AD673JN?
The AD673JN has a maximum conversion time of 30 µs, enabling a theoretical maximum sampling rate of approximately 33 kSPS in continuous operation. However, practical throughput depends on external timing - the CONVERT pulse must allow ≥30 µs between falling edges, and DATA ENABLE must be asserted only after DATA READY goes low. For burst-mode acquisition, the AD673JN reliably sustains 50 kSPS when paired with fast microprocessor handshaking using the DR signal.
Does the AD673JN require external components to operate?
No - the AD673JN is a fully self-contained 8-bit ADC with integrated buried Zener reference, on-chip clock, comparator, SAR register, and 3-state output buffers. Only power supplies (+5 V and –12 V to –15 V), analog input signal, CONVERT trigger, and DATA ENABLE control are needed for basic operation. External components like trim pots are optional and used only for fine full-scale or offset calibration beyond the device's guaranteed ±1/2 LSB accuracy.
How do I configure the AD673JN for bipolar input range (–5 V to +5 V)?
To configure the AD673JN for bipolar operation, leave Pin 16 (BIPOLAR OFFSET) unconnected (open). This enables internal offset current injection that shifts the transfer function so that –5 V produces output code 00000000, 0 V yields 10000000, and +4.961 V gives 11111111. No external resistors or switches are required - the mode is purely determined by the DC state of Pin 16, and the output coding automatically switches to positive true offset binary.
What is the purpose of separate ANALOG COMMON and DIGITAL COMMON pins on the AD673JN?
The AD673JN uses separate ANALOG COMMON (Pin 11) and DIGITAL COMMON (Pin 3) to isolate analog signal return paths from digital switching noise. ANALOG COMMON carries up to 2 mA transient current during conversion and must be decoupled independently; DIGITAL COMMON serves as the reference for logic inputs/outputs. The two commons may differ by up to ±200 mV - allowing flexible PCB grounding strategies while preventing digital noise from modulating the analog input accuracy.
Can the AD673JN interface directly with an 8085 microprocessor without additional logic?
Yes - the AD673JN is designed for direct 8085 interface: its CONVERT input can be driven by the processor's WR signal (gated with address decode), DATA ENABLE by RD, and DATA READY can be polled or used to generate an interrupt. The 8-bit TTL-compatible outputs (DB0–DB7) connect directly to the data bus, and timing parameters (e.g., 250 ns max tDD, 50 ns tHD) align with 8085 bus cycle specifications - eliminating need for latches, buffers, or wait-state generators in standard configurations.
AD673JN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Bits:
- 8
- Sampling Rate (Per Second):
- 33k
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- Parallel
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 1
- Architecture:
- -
- Reference Type:
- -
- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 20-PDIP
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
AD673JN FAQ
1.How can I place an order for AD673JN through Aetrix?
Please submit a Request for Quotation (RFQ) for AD673JN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD673JN reliable?
The price and inventory of AD673JN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD673JN is usually 5 days.
3.What payment methods are accepted for AD673JN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD673JN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD673JN?
AD673JN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD673JN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD673JN?
For technical support, including AD673JN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD673JN requirements.
6.How does Aetrix verify that AD673JN is sourced from the original manufacturer or authorized distributors?
All AD673JN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD673JN meets industry standards.
7.What is the process for return or replacement of AD673JN?
All AD673JN units undergo pre-shipment inspection (PSI). If there is an issue with AD673JN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD673JN part is unused and in its original packaging.
Return procedure for AD673JN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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