Analog Devices Inc. AD674BARZ

Overview

AD674BARZ from Analog Devices is a complete monolithic 12-bit successive-approximation analog-to-digital converter (ADC) with on-chip 10 V reference, clock generator, and three-state digital output buffers. It supports ±5 V/±10 V bipolar and 0 V–10 V/0 V–20 V unipolar input ranges, operates from +5 V logic and ±12 V/±15 V analog supplies, and delivers 15 µs max conversion time across –40°C to +85°C. It is used in precision industrial data acquisition systems requiring calibrated, self-contained ADC functionality without external timing or reference components.

For engineers reviewing the AD674BARZ datasheet, AD674BARZ pinout, AD674BARZ application, or AD674BARZ equivalent, this page provides verified technical context, exact pin functions, real-world interface constraints (e.g., dynamic analog input loading at ~1 MHz), calibrated input range behavior, and validated drop-in alternatives for legacy AD574A-based designs.

Technical Context

The AD674BARZ implements a SAR architecture with internal 12-bit current-output DAC, comparator, and laser-trimmed thin-film resistor network for scaling and bipolar offset. Its analog front-end includes dedicated 10 VIN and 20 VIN inputs with programmable span selection via external connections-not internal register control.

Digital interface supports both full 12-bit word reads and byte-mode (8-bit + 4-bit) access via A0 and 12/8 pins, with CE-active-HIGH, CS-active-LOW, and R/C dual-function (LOW = convert, HIGH = read in full-control mode). Status flag (STS) goes LOW upon conversion completion, enabling interrupt-driven data capture.

Key Specifications

Pinout & Package

AD674BARZ is supplied in a 28-pin plastic SOIC package (R-28), with gull-wing leads, JEDEC MS-012AC compliant, body size 17.9 mm × 7.5 mm × 2.3 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 12-bit SAR ADC applications.

Compared with AD674BJN, AD674BARZ offers extended temperature range and surface-mount compatibility; compared with AD1674KN, it trades integrated sampling for lower power and simpler biasing, making it preferable for DC or low-frequency (<10 kHz) precision measurement where external S/H is already present.

Availability

AD674BARZ is available at Aetrix Electronics and suitable for industrial process monitoring, test & measurement instrumentation, avionics sensor interfaces, and legacy industrial control retrofit programs requiring stable component supply and long-lifecycle support.

Supply support for AD674BARZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD674B product line was engineered as a pin-compatible, higher-speed, lower-power evolution of the industry-standard AD574A-targeting precision data acquisition in industrial, military, and aerospace systems where self-contained calibration and wide temperature operation are essential.

FAQ

What is the maximum conversion rate supported by the AD674BARZ?

The AD674BARZ has a maximum conversion time of 15 µs, enabling a theoretical maximum sustained sampling rate of approximately 66.7 kSPS. However, actual achievable throughput depends on bus access timing-minimum CE pulsewidth is 50 ns, and read cycle access time is 150 ns-so practical rates in microprocessor interfaces are typically 40–50 kSPS with proper wait-state management. The AD674BARZ does not support continuous auto-conversion mode; each conversion must be explicitly initiated via R/C or CE control.

Can the AD674BARZ operate with only +5 V and ground, omitting negative supplies?

No, the AD674BARZ requires three independent supplies: +5 V (VLOGIC), +12 V or +15 V (VCC), and –12 V or –15 V (VEE). The analog section uses dual-supply op-amp topology internally; removing VEE disables the comparator, DAC biasing, and bipolar input capability. Attempting operation with only +5 V and ground will result in non-functional or undefined behavior-particularly failure to complete conversions or erratic STS output. The datasheet specifies absolute maximum ratings down to –16.5 V on VEE, confirming mandatory negative rail usage.

How does the AD674BARZ handle analog input impedance variation between 10 V and 20 V span modes?

The AD674BARZ presents different input impedances depending on selected span: 5 kΩ (typ) at 10 VIN pin for 0 V–10 V/–5 V–+5 V ranges, and 10 kΩ (typ) at 20 VIN pin for 0 V–20 V/–10 V–+10 V ranges. These values are fixed by internal thin-film resistor dividers and do not change with input voltage. Designers must ensure driving source impedance is ≤100 Ω to avoid gain error-especially critical in bipolar modes where offset errors compound. The impedance is purely resistive; no capacitive component is specified, simplifying anti-alias filter design.

Is external trimming required for the AD674BARZ to meet its specified accuracy?

External trimming is optional but not required for baseline specification compliance. The AD674BARZ is factory laser-trimmed for unipolar offset (≤2 LSB), full-scale calibration (≤0.25% FS), and linearity (≤1 LSB). If system-level accuracy demands tighter than ±1 LSB zero error or <0.1% FS gain error, the offset trim (R1) and full-scale trim (R2) points shown in Figures 7–8 can be used-applying a 50 Ω resistor between REF OUT and REF IN is sufficient for most applications. No trimming is needed for basic 12-bit digitization tasks within datasheet limits.

What is the role of the STS pin, and how should it be interfaced in an interrupt-driven system?

The STS (Status) pin is an open-collector–compatible digital output that goes HIGH at conversion start and transitions LOW within 225 ns after conversion completion. In interrupt-driven systems, STS should be connected to a microcontroller's external interrupt input (with pull-up resistor) to trigger ISR execution immediately upon data readiness. Because STS is asynchronous to the host clock, debouncing is unnecessary; however, reading DB11–DB0 must occur only after STS has gone LOW and sufficient hold time (25 ns min) has elapsed. Using STS avoids polling overhead and ensures deterministic latency between conversion end and data capture.