Analog Devices Inc. AD676BD

Overview

AD676BD from Analog Devices is a 16-bit successive-approximation analog-to-digital converter (SAR ADC) with on-chip sample-hold, autocalibration, and parallel digital output. It delivers 100 kSPS conversion rate (10 µs total time), ±1.5 LSB integral nonlinearity, 87 dB S/(N+D) at 83 kSPS, and operates from ±12 V analog and +5 V digital supplies. It is used in precision instrumentation and data acquisition systems requiring stable dc accuracy and dynamic performance.

For engineers reviewing the AD676BD datasheet, AD676BD pinout, AD676BD application, or AD676BD equivalent, key selection considerations include its bipolar input range (±VREF), ceramic 28-pin DIP package, –40°C to +85°C industrial temperature grade, and requirement for external 5–10 V reference voltage.

Technical Context

The AD676BD implements a switched-capacitor charge-redistribution SAR architecture segmented across two monolithic chips-an analog BiMOS II ADC die and a digital DSP CMOS controller die-housed in one ceramic DIP package. Its autocalibration uses an on-chip microcontroller and calibration DAC to measure and correct capacitor mismatch errors, storing correction values in RAM for real-time compensation.

Conversion is initiated by a falling edge on SAMPLE after a minimum high-time (tS = 2 µs), followed by exactly 17 CLK cycles. The device outputs twos-complement data on 16 parallel lines (BIT 1–BIT 16), with BUSY indicating active conversion or calibration, and supports continuous conversion mode when SAMPLE is reasserted before BUSY deasserts.

Key Specifications

Pinout & Package

AD676BD is housed in a 28-pin side-brazed ceramic DIP (package option D-28), providing hermetic sealing and thermal stability for demanding industrial deployments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit SAR ADC applications.

Compared with AD7606BSTZ and ADS8860IDRCT, the AD676BD offers superior dc accuracy stability over temperature and hermetic ceramic packaging for harsh environments, but lacks multi-channel capability or modern serial interfaces - making it ideal for retrofitting or mission-critical analog front-ends where long-term calibration integrity is paramount.

Availability

AD676BD is available at Aetrix Electronics and suitable for high-reliability data acquisition, industrial process control, and test equipment requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for AD676BD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The AD676BD belongs to Analog Devices' precision SAR ADC product line, engineered for applications demanding uncompromised dc accuracy, low distortion, and long-term calibration stability - especially where environmental stress and supply variation challenge alternative architectures.

FAQ

What is the guaranteed integral nonlinearity (INL) specification for AD676BD?

The AD676BD has a maximum integral nonlinearity of ±1.5 LSB over its full operating temperature range (–40°C to +85°C) and at 100 kSPS conversion rate. This value is specified post-autocalibration and reflects worst-case deviation from the ideal transfer function, ensuring consistent measurement fidelity in industrial instrumentation where absolute accuracy is critical. The AD676BD achieves this via on-chip capacitor mismatch correction stored in RAM.

Does AD676BD require an external voltage reference, and what range is supported?

Yes, the AD676BD requires an external precision voltage reference applied to the VREF pin. It supports a 5 V to 10 V input range, directly scaling the ±VREF analog input span. For example, a 10 V reference yields a ±10 V input range with 16-bit resolution (≈305 µV/LSB). Reference stability and low noise are essential - Analog Devices recommends using the REF02 or ADR435 with proper decoupling to maintain the AD676BD's 87 dB S/(N+D) performance.

How does the autocalibration function work in AD676BD, and when should it be performed?

The AD676BD performs autocalibration by measuring and correcting capacitor array mismatches using an on-chip microcontroller and calibration DAC. When CAL is pulsed LOW, it executes an 85,530-clock-cycle routine that nulls sample/hold offset and stores correction factors in RAM. Calibration is recommended at power-up after supplies and VREF stabilize; skipping it may reduce accuracy to ~10-bit level. Once calibrated, the AD676BD maintains specification without periodic recalibration under normal operating conditions.

What are the power supply requirements and decoupling recommendations for AD676BD?

The AD676BD requires three independent supplies: +12 V (VCC), –12 V (VEE), and +5 V (VDD), each with dedicated 0.1 µF ceramic bypass capacitors placed within 2 mm of their respective pins. VCC and VEE must be decoupled to AGND; VDD to DGND. A solid analog ground plane and single-point AGND–DGND connection near the AD676BD are mandatory. Large bulk capacitors (>47 µF) should be placed at PCB power entry points to suppress low-frequency ripple that could degrade the AD676BD's 360 mW typical power consumption performance.

Can AD676BD operate in continuous conversion mode, and how is timing managed?

Yes, the AD676BD supports continuous conversion mode by reasserting SAMPLE before BUSY goes LOW at the end of the prior conversion. This overlaps acquisition and conversion phases, enabling maximum throughput. Timing must respect tSL (min SAMPLE low time = 100 ns) and tSC (min delay from SAMPLE low to first CLK = 50 ns). Data from the previous conversion remains valid until BUSY falls or tOD (200 ns) after the 17th CLK rising edge - latching on BUSY's falling edge is strongly recommended to avoid metastability in the AD676BD's parallel output interface.