Analog Devices Inc. AD676-EB

Overview

AD676-EB from Analog Devices is a 16-bit successive-approximation analog-to-digital converter (SAR ADC) with on-chip sample-hold, autocalibration, and parallel digital output. It delivers 100 kSPS conversion rate, ±1 LSB INL (J-grade), –97 dB THD, 90 dB S/(N+D), and 1 MHz full-power bandwidth. It operates from +5 V and ±12 V supplies and is used in precision instrumentation, data acquisition systems, and automated test equipment.

For engineers reviewing the AD676-EB datasheet, AD676-EB pinout, AD676-EB application, or AD676-EB equivalent, key selection criteria include its 16-bit no-missing-codes performance, dual-chip BiMOS II/CMOS architecture, ac/dc specification coverage, and requirement for external 5–10 V reference voltage and precise timing control via SAMPLE/CLK signals.

Technical Context

The AD676-EB implements a switched-capacitor charge-redistribution SAR architecture-eliminating laser-trimmed resistor ladders-and integrates two monolithic chips: an analog ADC chip (BiMOS II) and a digital controller chip (DSP CMOS), both housed in one package. Its autocalibration uses an on-chip microcontroller and calibration DAC to measure and store capacitor mismatch corrections in RAM.

Conversion requires 17 clock cycles per sample, with strict timing dependencies: SAMPLE falling edge initiates acquisition, aperture delay is 6 ns, and maximum conversion time is 1000 µs to maintain specified accuracy. Output coding is twos complement, and BUSY provides asynchronous status signaling for latch synchronization.

Key Specifications

Pinout & Package

The AD676-EB is supplied in a 28-pin ceramic DIP package (package option D-28), with separate analog/digital grounds, dedicated AGND sense, and isolated power domains for VCC (+12 V), VEE (–12 V), and VDD (+5 V).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit SAR ADC applications.

Compared with AD7606-6 and ADS8860, the AD676-EB uniquely combines autocalibration, ±12 V analog supplies, and parallel 16-bit output in a single-chip-compatible ceramic DIP-making it optimal for legacy industrial systems requiring guaranteed dc accuracy without FPGA-based timing management.

Availability

AD676-EB is available at Aetrix Electronics and suitable for high-accuracy data acquisition, precision instrumentation, and automated test equipment requiring stable component supply and long-term obsolescence support.

Supply support for AD676-EB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD676 product line was designed for precision measurement and signal analysis applications demanding verified dc accuracy, low distortion, and robust operation across industrial temperature ranges-targeting systems where calibration stability and noise immunity are non-negotiable.

FAQ

What is the function of the CAL pin on the AD676-EB?

The CAL pin on the AD676-EB is an asynchronous digital input that triggers the on-chip autocalibration routine. When driven HIGH, it resets internal logic and asserts BUSY; when brought LOW, it initiates a 85,530-clock-cycle calibration sequence that measures and stores capacitor mismatch corrections in on-chip RAM. This process ensures ±1 LSB INL without external trims and is typically performed once at power-up after supplies stabilize. The AD676-EB must be calibrated to achieve full 16-bit accuracy-uncalibrated operation degrades performance to ~10 bits.

Does the AD676-EB require an external voltage reference, and what range is supported?

Yes, the AD676-EB requires an external precision voltage reference applied to the VREF pin. It supports 5 V to 10 V input range, with full-scale analog input defined as ±VREF. Performance specifications-including gain error (0.005% FSR), THD (–97 dB), and S/(N+D) (90 dB)-are guaranteed only when using a stable, low-noise reference within this range. The AD676-EB does not include an internal reference; using VREF = 10 V maximizes dynamic range and minimizes quantization-related noise floor impact. The AD676-EB reference input exhibits 160 µV rms noise and requires proper decoupling per Figure 4 in the datasheet.

How is timing controlled during conversion on the AD676-EB?

Timing on the AD676-EB is controlled by two digital inputs: SAMPLE and CLK. A conversion begins when SAMPLE transitions from HIGH to LOW, initiating the hold phase after a 6 ns aperture delay. Exactly 17 CLK rising edges then execute the SAR algorithm, with BUSY going LOW on the 17th edge to indicate valid output. Minimum timing constraints include tSL ≥ 100 ns (SAMPLE LOW duration), tSC ≥ 50 ns (delay before first CLK), and tC ≤ 1000 µs (max elapsed time from SAMPLE HIGH to 17th CLK). The AD676-EB ignores CLK edges before tSC and after BUSY goes LOW, ensuring deterministic, jitter-controlled sampling windows.

What are the power supply requirements for the AD676-EB?

The AD676-EB requires three independent supplies: VCC = +12 V ±5%, VEE = –12 V ±5%, and VDD = +5 V ±10%. VCC and VEE power the analog circuitry (SHA, ADC core), while VDD powers the digital controller and output buffers. Total typical power consumption is 360 mW (ICC = 14.5–18 mA, IEE = 14.5–18 mA, IDD = 2–5 mA). Decoupling mandates 0.1 µF ceramic capacitors placed within 2 mm of each supply pin, with analog (VCC/VEE/VREF) and digital (VDD/DGND) grounds separated except at a single-point package tie. The AD676-EB's PSRR is ±1 LSB for ±5% supply variation.

Can the AD676-EB operate in continuous conversion mode, and how is it configured?

Yes, the AD676-EB supports continuous conversion mode by reasserting SAMPLE HIGH immediately after BUSY goes LOW-enabling overlapping acquisition and conversion cycles. In this mode, the next sample is acquired during the final CLK cycle of the current conversion, maximizing throughput to 100 kSPS. To implement it, SAMPLE must remain HIGH long enough to satisfy tS ≥ 2 µs acquisition time, and timing margins (tSB, tBS, tOD) must still be met. Latching of previous conversion data should occur on or after the falling edge of BUSY. The AD676-EB's continuous mode is commonly clocked using a counter-derived SAMPLE signal (e.g., 74HC393 dividing a 12.288 MHz system clock), and the AD676-EB maintains full 16-bit accuracy in this configuration when timing specs are observed.