Analog Devices Inc. AD676JD

Overview

AD676JD from Analog Devices is a 16-bit successive-approximation analog-to-digital converter (SAR ADC) with on-chip sample-hold, autocalibration, and parallel digital output. It delivers 100 kSPS conversion rate (10 µs total time), ±1 LSB INL (J-grade), –97 dB THD, and 90 dB S/(N+D) at 100 kSPS - enabling precision dc measurement and ac signal processing in instrumentation and data acquisition systems.

For engineers reviewing the AD676JD datasheet, AD676JD pinout, AD676JD application, or AD676JD equivalent, key selection considerations include its dual-chip BiMOS II + DSP CMOS architecture, ±12 V / +5 V triple-supply operation, 28-pin ceramic DIP package, and requirement for external 5–10 V reference voltage to achieve specified dynamic performance.

Technical Context

The AD676JD implements a capacitor-array charge redistribution SAR architecture - eliminating laser-trimmed resistor ladders and reducing temperature-induced linearity drift. Its analog and digital functions are partitioned across two monolithic dies (BiMOS II analog ADC + DSP CMOS controller) co-packaged in one ceramic DIP.

Autocalibration uses an on-chip microcontroller and calibration DAC to measure and store capacitor mismatch corrections in RAM; this enables ±1 LSB INL without user trims. Conversion is initiated by SAMPLE high-to-low edge, synchronized to 17 CLK cycles, with BUSY signaling active conversion or calibration.

Key Specifications

Pinout & Package

AD676JD is housed in a 28-pin side-brazed ceramic DIP (package option D-28), with pins arranged in dual in-line configuration and lid internally connected to VEE (Pin 17).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit SAR ADC applications.

Compared with AD7656ASTZ and ADS8860IDRCT, the AD676JD provides superior dc precision (±1 LSB INL) and integrated analog functionality (sample-hold, autocalibration, dual-supply isolation), making it optimal for lab-grade measurement where absolute accuracy and ease of analog interface dominate over channel count or speed.

Availability

AD676JD is available at Aetrix Electronics and suitable for high-accuracy data loggers, automated test equipment, industrial process monitors, medical instrumentation, and precision sensor interfaces requiring stable component supply and long-lifecycle support.

Supply support for AD676JD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD676JD belongs to Analog Devices' precision SAR ADC product line, designed specifically for applications demanding high dc accuracy, low distortion, and simplified analog front-end integration in industrial and instrumentation systems.

FAQ

What is the operating temperature range for the AD676JD?

The AD676JD is rated for 0°C to +70°C ambient operation (J-grade). This range is validated per the ordering guide and applies to all ac and dc specifications including ±1 LSB INL, –97 dB THD, and 90 dB S/(N+D) at 100 kSPS. Operation outside this range may degrade performance and is not guaranteed by Analog Devices.

Does the AD676JD require an external voltage reference, and what range is supported?

Yes, the AD676JD requires an external precision voltage reference applied to the VREF pin. It supports 5 V to 10 V input range, with full dynamic performance (e.g., 90 dB S/(N+D)) specified at VREF = 10.0 V. Using VREF = 5.0 V reduces full-scale range but maintains 16-bit resolution and no missing codes.

How does autocalibration work in the AD676JD, and how often must it be performed?

The AD676JD performs on-chip autocalibration by measuring capacitor mismatches using an internal calibration DAC and storing correction values in RAM. Calibration is triggered by asserting CAL HIGH then LOW and completes in 85,530 clock cycles. For most applications, calibrating once at power-up - after supplies and VREF stabilize - is sufficient; uncalibrated operation degrades accuracy to ~10-bit level.

What are the critical PCB layout requirements for the AD676JD to achieve specified performance?

To achieve ±1 LSB INL and 90 dB S/(N+D), the AD676JD requires strict layout: separate analog (AGND) and digital (DGND) ground planes joined at a single point near Pin 11 and Pin 13; 0.1 µF ceramic decoupling capacitors placed within 2 mm of each supply pin (VCC, VEE, VDD, VREF); and routing of VIN, VREF, and AGND SENSE away from digital traces, crossing only at right angles.

Can the AD676JD interface directly with a 16-bit microprocessor data bus?

Yes, the AD676JD provides parallel 16-bit twos-complement output (Pins 1–6 and 19–28) compatible with standard 16-bit data buses. BUSY (Pin 7) serves as a ready signal to latch data; timing diagrams in the datasheet confirm valid data window after BUSY goes LOW and before the 17th CLK cycle. No level-shifting is needed for +5 V logic families.