Analog Devices Inc. AD676JNZ

Overview

AD676JNZ from Analog Devices is a 16-bit successive-approximation analog-to-digital converter (SAR ADC) with on-chip sample-hold, autocalibration, and parallel digital output. It delivers 100 kSPS conversion rate (10 µs total time), ±1 LSB INL (J-grade), –97 dB THD, and 90 dB S/(N+D) at 100 kSPS, operating from +5 V, ±12 V supplies in precision measurement systems.

For engineers reviewing the AD676JNZ datasheet, AD676JNZ pinout, AD676JNZ application, or AD676JNZ equivalent, key selection considerations include its 28-pin ceramic DIP package, dual-chip BiMOS II/CMOS architecture, 1 MHz full-power bandwidth, bipolar input range (±VREF), and requirement for external 5–10 V reference voltage.

Technical Context

The AD676JNZ implements a switched-capacitor charge-redistribution SAR architecture-replacing laser-trimmed resistor ladders with binary-weighted capacitors to eliminate temperature-induced linearity drift. Its two-die construction separates analog signal processing (BiMOS II) from digital control (DSP CMOS), minimizing crosstalk.

Autocalibration uses an on-chip microcontroller and calibration DAC to measure and store capacitor mismatch corrections in RAM, enabling ±1 LSB INL without user trim. Conversion is initiated by SAMPLE high→low edge, requires 17 CLK cycles, and outputs twos-complement data via 16-bit parallel bus with BUSY status signaling.

Key Specifications

Pinout & Package

AD676JNZ is housed in a 28-pin side-brazed ceramic DIP (package option D-28), with isolated analog/digital ground pins (AGND, DGND), analog ground sense (AGND SENSE), and dedicated power pins for analog (VCC, VEE) and digital (VDD) domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit SAR ADC applications.

Compared with AD7606BSTZ and ADS8860IDRCT, AD676JNZ uniquely combines autocalibration, bipolar ±VREF input, and dual-supply isolation in a 28-pin DIP-making it optimal for legacy industrial and test systems prioritizing long-term DC accuracy over channel count or power efficiency.

Availability

AD676JNZ is available at Aetrix Electronics and suitable for high-accuracy data acquisition, industrial process monitoring, and medical instrumentation requiring stable component supply and long-lifecycle support.

Supply support for AD676JNZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and signal conditioning.

The AD676JNZ belongs to Analog Devices' precision SAR ADC product line, designed specifically for applications demanding guaranteed 16-bit no-missing-codes performance, on-chip calibration, and robust operation in noisy industrial environments.

FAQ

What is the maximum recommended conversion time for AD676JNZ to maintain specified accuracy?

The AD676JNZ specifies a maximum conversion time (tC) of 1000 µs from SAMPLE high to completion of the 17th CLK pulse. Exceeding this interval risks degradation of dc accuracy due to leakage in internal storage capacitors used for error correction. For guaranteed ±1 LSB INL and 90 dB S/(N+D), all conversions must complete within this window. The typical conversion time is 10 µs at 100 kSPS, but system clock variations or timing margin violations may extend it toward the limit.

Does AD676JNZ require an external voltage reference, and what range is supported?

Yes, AD676JNZ requires an external voltage reference applied to the VREF pin. It supports 5 V to 10 V input range, with full-scale analog input defined as ±VREF. Performance specifications-including INL, THD, and S/(N+D)-are validated at VREF = 10.0 V. Using 5 V reference reduces full-scale range but maintains 16-bit resolution; however, dynamic performance degrades slightly (e.g., S/(N+D) drops to 85 dB). Reference stability and noise directly impact gain error and SNR.

How does the autocalibration function of AD676JNZ operate, and when should it be performed?

AD676JNZ autocalibration measures and corrects capacitor mismatch errors using an on-chip microcontroller and calibration DAC, storing correction factors in RAM. It is triggered asynchronously by taking CAL HIGH then LOW, completing in 85,530 clock cycles. Calibration is recommended at power-up after supplies and VREF stabilize. Without calibration, accuracy degrades to ~10-bit level. Subsequent calibrations are optional but advised after large temperature shifts or long idle periods to maintain ±1 LSB INL.

What are the critical layout requirements for AD676JNZ to achieve specified dynamic performance?

To achieve –97 dB THD and 90 dB S/(N+D), AD676JNZ requires strict layout practices: separate analog (AGND) and digital (DGND) ground planes joined at a single point near the IC; 0.1 µF ceramic decoupling capacitors placed within 2 mm of each supply pin (VCC, VEE, VDD); AGND SENSE routed as a dedicated Kelvin trace; and VIN/VREF traces shielded from digital routing. Board trace impedance must be <0.1 Ω to avoid >1 LSB voltage drop under 1.22 mA current-critical for 16-bit accuracy at 10 V full scale.

Can AD676JNZ interface directly with a 3.3 V microprocessor data bus?

No, AD676JNZ digital outputs are CMOS-compatible with VDD = +5 V and specify VOH ≥ 2.4 V at IOL = 0.5 mA, making direct connection to 3.3 V logic unsafe without level translation. Its output drivers are not 5 V-tolerant in 3.3 V systems, and interfacing without a level shifter risks violating VIH/VIL thresholds of 3.3 V receivers. A bidirectional level translator (e.g., TXB0108) or 5 V-tolerant FPGA I/O bank is required to maintain signal integrity and prevent damage to downstream logic.