Analog Devices Inc. AD7352BRUZ

Overview

AD7352BRUZ from Analog Devices is a dual, 12-bit, successive approximation register (SAR) analog-to-digital converter with simultaneous sampling, 3 MSPS per channel throughput, differential input architecture, on-chip 2.048 V reference, and operation over −40°C to +125°C. It targets high-fidelity data acquisition in motion control and I/Q demodulation systems requiring matched channel timing and low inter-channel crosstalk.

For engineers reviewing the AD7352BRUZ datasheet, AD7352BRUZ pinout, AD7352BRUZ application, or AD7352BRUZ equivalent, key selection considerations include simultaneous dual-channel sampling latency, ADC-to-ADC isolation (−100 dB), differential input common-mode range (0.5 V to 1.9 V), SPI-compatible serial interface timing, and TSSOP-16 package thermal performance (θJA = 143°C/W).

Technical Context

The AD7352BRUZ integrates two independent SAR ADCs sharing a single 2.5 V VDD supply and internal 2.048 V reference, each with dedicated track-and-hold amplifiers supporting >110 MHz full-power bandwidth. Conversion is initiated on the falling edge of CS, with no conversion latency and deterministic timing governed by SCLK frequency (up to 48 MHz).

It supports three power modes-Normal (26 mW at 3 MSPS), Partial Power-Down (9.5 mW), and Full Power-Down (16 μW)-with flexible VDRIVE (2.25–3.6 V) for logic-level compatibility. Analog inputs are fully differential (VINA±, VINB±), referenced to AGND, with strict ground separation requirements (AGND–DGND ≤ ±0.3 V).

Key Specifications

Pinout & Package

AD7352BRUZ is housed in a 16-lead Thin Shrink Small Outline Package (TSSOP) with 0.65 mm pitch, 5.0 mm × 4.4 mm body, and θJA = 143°C/W. The package supports reflow soldering per JEDEC J-STD-020 (peak 255°C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel SAR ADC applications.

Compared with AD7352BRUZ, AD7356BRUZ trades lower power (26 mW → 45 mW) for +2 MSPS throughput, while AD7357BRUZ adds 2 bits of resolution at +29 mW and +0.8 MSPS-both retain simultaneous sampling but require VDD upgrade from 2.5 V to 3.3 V.

Availability

AD7352BRUZ is available at Aetrix Electronics and suitable for motion control feedback, I/Q demodulation, and industrial sensor monitoring requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.

Supply support for AD7352BRUZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The AD7352BRUZ belongs to Analog Devices' precision dual SAR ADC product line, engineered for applications demanding time-aligned, low-latency, and low-crosstalk digitization of differential analog signals in thermally demanding environments.

FAQ

What is the maximum sampling frequency supported by the AD7352BRUZ?

The AD7352BRUZ supports a maximum throughput rate of 3 MSPS per channel. This is achieved with a 48 MHz SCLK and fixed 13-cycle conversion time. At this rate, the device delivers 71.5 dB SNR and maintains ±0.99 LSB DNL. The AD7352BRUZ does not support oversampling or decimation modes; its 3 MSPS is the hard limit for simultaneous dual-channel operation.

Does the AD7352BRUZ require an external reference voltage?

No, the AD7352BRUZ includes an integrated 2.048 V reference with ±0.25% initial accuracy and 6 ppm/°C temperature coefficient. REFA and REFB pins provide access to this reference and accept external overdrive voltages from 2.148 V to VDD. External references are optional and used only when system-level voltage scaling or tighter drift specs are needed beyond the on-chip reference capabilities.

How is simultaneous sampling implemented in the AD7352BRUZ?

The AD7352BRUZ implements simultaneous sampling using two independent track-and-hold amplifiers-one per ADC channel-that share a common CS control signal. On the falling edge of CS, both THAs freeze their inputs at the exact same instant, achieving aperture delay match ≤40 ps. This hardware-synchronized acquisition ensures phase coherence between channels without software intervention or clock skew compensation.

What are the power supply requirements for the AD7352BRUZ?

The AD7352BRUZ requires two supplies: VDD = 2.5 V ±10% (2.25 V to 2.75 V) for the analog core and VDRIVE = 2.25 V to 3.6 V for digital I/O. VDD and VDRIVE must be decoupled separately-VDD to AGND with 0.1 µF + 10 µF, VDRIVE to DGND with identical capacitance. AGND and DGND must remain within ±0.3 V potential difference to avoid noise injection into the analog path.

Can the AD7352BRUZ interface directly with an FPGA using SPI protocol?

Yes, the AD7352BRUZ features a SPI-/QSPI™-/MICROWIRE™-/DSP-compatible serial interface with CS, SCLK, SDATAA, and SDATAB. It operates in standard SPI Mode 3 (CPOL = 1, CPHA = 1), outputs MSB-first with two leading zeros, and requires 14 SCLK cycles per 12-bit word. The FPGA can read both channels concurrently via separate data lines or sequentially on one line using 16-cycle framing-no level-shifting needed if VDRIVE matches FPGA I/O voltage.