Analog Devices Inc. AD7367BRUZ-5

Overview

AD7367BRUZ-5 from Analog Devices is a dual-channel, 14-bit, simultaneous-sampling SAR ADC with true bipolar ±10 V/±5 V/0 V to +10 V analog inputs, 500 kSPS throughput, and on-chip 2.5 V ±0.2% reference. It operates across −40°C to +85°C and targets precision industrial data acquisition systems requiring synchronized voltage monitoring of motor phases or sensor pairs.

For engineers reviewing the AD7367BRUZ-5 datasheet, AD7367BRUZ-5 pinout, AD7367BRUZ-5 application, or AD7367BRUZ-5 equivalent, key selection criteria include simultaneous dual-channel conversion timing (≤1.25 μs), channel-to-channel isolation (−90 dB), SNR (76 dB at 50 kHz), input impedance (500 kΩ @ ±10 V, 500 kSPS), and TSSOP-24 package compatibility with high-voltage analog signal chains.

Technical Context

The AD7367BRUZ-5 integrates two independent 14-bit SAR ADC cores, each preceded by a track-and-hold amplifier and fed via a 2-channel multiplexer per ADC. Its iCMOS process enables ±16.5 V analog supply rails (VDD/VSS) while maintaining low power consumption (4–5.45 mW operational).

It supports SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface with MSB-first 14-bit data output on DOUTA/DOUTB, programmable input ranges via RANGE0/RANGE1 pins, and internal/external reference selection via REFSEL. Conversion is initiated by CNVST falling edge, with BUSY indicating active conversion.

Key Specifications

Pinout & Package

AD7367BRUZ-5 is housed in a 24-lead TSSOP package with exposed pad (RoHS-compliant, JEDEC MO-153). Pin layout supports separate analog/digital grounds (AGND ×2, DGND), dual analog input pairs (VA1/VA2, VB1/VB2), dedicated decoupling pins (DCAPA/DCAPB), and SPI-compatible control (CS, SCLK, CNVST, BUSY, ADDR, RANGE0/RANGE1, REFSEL).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, simultaneous-sampling ADC applications.

Compared with AD7367BRUZ-5, AD7366BRUZ-5 trades 2 bits of resolution and 4 dB SNR for lower cost and identical footprint, while ADS8684IPWR offers +2 bits but demands external level-shifting for ±10 V signals - making AD7367BRUZ-5 optimal for drop-in bipolar industrial upgrades.

Availability

AD7367BRUZ-5 is available at Aetrix Electronics and suitable for industrial motor control, power quality monitoring, and PLC analog input modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant TSSOP packaging.

Supply support for AD7367BRUZ-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD7367BRUZ-5 belongs to the AD7366/AD7367 family of dual-channel simultaneous-sampling SAR ADCs, designed specifically for industrial automation systems demanding true bipolar input capability, high channel isolation, and robust operation across −40°C to +85°C.

FAQ

What is the maximum analog input voltage range supported by the AD7367BRUZ-5?

The AD7367BRUZ-5 supports true bipolar analog input ranges of ±10 V, ±5 V, and 0 V to +10 V, all programmable via RANGE0 and RANGE1 pins. With an external 3 V reference applied to DCAPA/DCAPB and minimum ±12 V supplies (VDD ≥ +12 V, VSS ≤ −12 V), it accepts ±12 V inputs. Absolute input limits are VSS − 0.3 V to VDD + 0.3 V per the datasheet absolute maximum ratings.

Does the AD7367BRUZ-5 require external decoupling capacitors, and if so, where?

Yes, the AD7367BRUZ-5 requires external decoupling capacitors: 10 μF + 100 nF on AVCC and DVCC (pins 8 and 3), 10 μF + 100 nF on VDD (pin 15) and VSS (pin 10), and 680 nF on DCAPA (pin 9) and DCAPB (pin 16). These are mandatory for stable reference buffering, analog core operation, and digital interface integrity - omission degrades SNR and increases THD.

How does the AD7367BRUZ-5 achieve simultaneous sampling across both ADC channels?

The AD7367BRUZ-5 achieves simultaneous sampling using two independent track-and-hold amplifiers - one per ADC - sharing a common CNVST signal. On the CNVST falling edge, both T/H circuits enter hold mode at the same instant, freezing their respective analog inputs before conversion begins. Aperture delay matching is specified at ±100 ps, ensuring sub-100 ps timing skew between channels.

Can the AD7367BRUZ-5 operate with only a single 5 V supply?

No. The AD7367BRUZ-5 requires three distinct supply domains: AVCC/DVCC = 4.75–5.25 V (analog/digital core), VDRIVE = 2.7–5.25 V (interface logic), and split analog supplies VDD ≥ +5 V and VSS ≤ −5 V (up to ±16.5 V). A single 5 V rail cannot satisfy the high-voltage analog input structure - VDD and VSS must be independently biased to support ±10 V inputs.

What is the serial interface timing requirement for reading conversion data from the AD7367BRUZ-5?

The AD7367BRUZ-5 requires 14 SCLK cycles to read one 14-bit result per DOUT pin. SCLK frequency must be 10 kHz to 20 MHz. After BUSY falls, CS must be held low for ≥10 ns before SCLK starts (t4), and a minimum quiet time of 50 ns (tQUIET) is required between the end of one read and the next CNVST trigger. Data is valid on the SCLK falling edge with 7 ns hold time (t6).