Analog Devices Inc. AD7575JR

Overview

AD7575JR from Analog Devices is an 8-bit successive approximation analog-to-digital converter (ADC) with integrated track-and-hold, single +5 V supply operation, 5 µs conversion time, ±1 LSB total unadjusted error, and 0 to +70°C temperature range. It digitizes full-scale signals up to 50 kHz in microprocessor-based data acquisition systems.

For engineers reviewing the AD7575JR datasheet, AD7575JR pinout, AD7575JR application, or AD7575JR equivalent, key selection considerations include its LC2MOS process, 18-lead SOIC package, unipolar 0–2.46 V input range with 1.23 V reference, and compatibility with Z80H, 8085A-2, and TMS32010 processors via Slow Memory or ROM interface modes.

Technical Context

The AD7575JR uses a successive approximation register (SAR) architecture with on-chip DAC and comparator, synchronized by internal or external 4 MHz clock (divided-by-2 internally). Conversion begins on CS and RD low assertion, with sampling fixed at the third falling CLK edge.

Its track-and-hold function operates autonomously without external hold capacitor, supporting 386 mV/µs slew rate and enabling accurate digitization of 50 kHz full-scale sine waves. Interface logic supports memory-mapped access with BUSY-driven wait-state or non-blocking ROM-style dual-read sequencing.

Key Specifications

Pinout & Package

AD7575JR is housed in an 18-lead small-outline integrated circuit (SOIC) package (R-18), with gull-wing leads, 0.3-inch body width, and standard JEDEC MS-012AC footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit SAR ADC applications.

Compared with MAX160BCNG+ and ADS7822U, the AD7575JR uniquely integrates track-and-hold and parallel 8-bit bus interface in a single +5 V SOIC package-making it optimal for legacy microprocessor systems needing minimal external components and guaranteed 50 kHz signal fidelity.

Availability

AD7575JR is available at Aetrix Electronics and suitable for industrial data acquisition, embedded microcontroller systems, audio signal digitization, and test & measurement instrumentation requiring stable component supply across extended product lifecycles.

Supply support for AD7575JR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD7575JR belongs to Analog Devices' LC2MOS precision ADC family, designed specifically for microprocessor-centric data acquisition where integration, speed, and single-supply operation reduce system complexity in industrial and instrumentation applications.

FAQ

What is the maximum analog input frequency supported by the AD7575JR without amplitude error?

The AD7575JR supports full-scale signals up to 50 kHz with ≤1 LSB error, corresponding to a 386 mV/µs slew rate limit. This is verified for 2.46 V_PP sine waves at +25°C per Figure 11 and Table specifications. Operation beyond 50 kHz may introduce slewing-induced distortion even if Nyquist criteria are met, due to finite track-and-hold acquisition bandwidth.

Does the AD7575JR require external calibration for ±1 LSB accuracy?

No, the AD7575JR achieves ±1 LSB total unadjusted error over 0°C to +70°C without calibration. Its zero, full-scale, and linearity errors are inherently low per Rev. B specifications-offset error is ±0.5 LSB max and relative accuracy is ±0.5 LSB max. Calibration is optional and only needed for applications demanding sub-LSB precision.

Can the AD7575JR operate with an internal clock, and what are the trade-offs?

Yes, the AD7575JR supports internal clocking using RCLK = 100 kΩ and CCLK = 100 pF, yielding ~5 µs nominal conversion at +25°C. However, unit-to-unit variation can cause ±50% frequency spread, leading to conversion times from ~2.5 µs to 7.5 µs. For deterministic timing or tight software loops, an external 4 MHz clock is recommended to guarantee 5 µs performance.

How should the TP pin be handled in a production AD7575JR circuit?

The TP (Test Pin) on the AD7575JR must be hard-wired to VDD (+5 V) in all operational circuits. It is not a functional I/O and serves only for factory testing. Leaving TP floating or connecting it to any other node-including ground or signal lines-may cause undefined behavior or conversion failure. The datasheet explicitly warns against using TP as a feedthrough in double-sided PCBs.

What is the correct interface sequence to read valid data from the AD7575JR in ROM mode?

In ROM mode, issue two consecutive READ instructions to the AD7575JR address: the first initiates conversion and returns stale data (disregard), while the second reads the newly converted result. Ensure ≥5 µs delay between CS/RD assertions-i.e., the second READ must occur after BUSY goes high. If CS/RD go low within one CLK period of BUSY rising, a second conversion is suppressed and only data read occurs.