Analog Devices Inc. AD7626BCPZ

Overview

AD7626BCPZ from Analog Devices is a 16-bit, 10 MSPS differential successive approximation register (SAR) analog-to-digital converter with ±0.45 LSB INL, 91.5 dB SNR, and ±4.096 V differential input range. It features LVDS serial output, internal 4.096 V reference, and operates in self-clocked or echoed clock mode for high-speed data acquisition in digital imaging and spectrum analysis systems.

For engineers reviewing the AD7626BCPZ datasheet, AD7626BCPZ pinout, AD7626BCPZ application, or AD7626BCPZ equivalent, this page delivers verified technical context, real-world interface timing, package-specific layout guidance, and validated alternative options for high-dynamic-range signal chain design.

Technical Context

The AD7626BCPZ implements a charge redistribution SAR architecture with no pipeline latency, enabling deterministic 100 ns conversion cycle time and zero-cycle dead time between samples. Its differential antiphase input stage supports true bipolar operation with 95 MHz −3 dB input bandwidth and 0.25 ps rms aperture jitter.

It integrates dual supply domains (5 V analog, 2.5 V digital/I/O), on-chip reference buffer, and configurable LVDS interface with DCO± clock echo or self-clocked framing. The 32-lead LFCSP package includes dedicated CAP1/CAP2 pins for precision decoupling of internal bandgap and reference circuitry.

Key Specifications

Pinout & Package

AD7626BCPZ is housed in a 32-lead, 5 mm × 5 mm LFCSP (CP-32-7) with exposed thermal pad. Pin 1 is located at top-left per JEDEC MO-220; the exposed pad must be connected to PCB ground plane via ≥4 thermal vias.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with AD7626BCPZ, AD7623BCPZ trades 0.8 LSB INL and 2.5 dB SNR for lower cost, while AD7960BCPZ doubles resolution at half throughput and requires external reference - making AD7626BCPZ optimal for balanced speed/linearity in imaging and spectrum analysis.

Availability

AD7626BCPZ is available at Aetrix Electronics and suitable for digital imaging systems, high-speed spectrum analyzers, and telecom IF receivers requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD7626BCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD7626BCPZ belongs to Analog Devices' PulSAR® family of high-speed SAR ADCs, designed specifically for applications demanding both high resolution and high throughput without pipeline latency - such as medical imaging, test equipment, and communications infrastructure.

FAQ

What is the maximum sample rate supported by the AD7626BCPZ?

The AD7626BCPZ supports a maximum throughput rate of 10 MSPS, corresponding to a minimum conversion cycle time of 100 ns. This is achievable in both self-clocked and echoed clock LVDS interface modes, with valid data available within 100 ns after the CNV edge. At 10 MSPS, the device maintains 91.5 dB SNR and ±0.45 LSB INL across the full −40°C to +85°C operating range. The AD7626BCPZ achieves this performance using a charge redistribution SAR architecture with no pipeline delay.

Does the AD7626BCPZ require an external reference voltage?

No, the AD7626BCPZ does not require an external reference voltage - it includes an internal 4.096 V buffered reference that can be enabled via EN1/EN0 pin configuration (EN1 = EN0 = 1). Alternatively, it supports external 1.2 V applied to REFIN or external 4.096 V applied to REF. When using the internal reference, the AD7626BCPZ delivers 91.5 dB SNR and ±0.45 LSB INL. The AD7626BCPZ's reference flexibility allows optimization for noise, power, or system-level calibration requirements.

What is the purpose of the DCO+ and DCO− pins on the AD7626BCPZ?

The DCO+ and DCO− pins on the AD7626BCPZ provide LVDS-buffered clock outputs used to synchronize data capture in the host system. When DCO+ is grounded, the AD7626BCPZ enters self-clocked mode and outputs a 2-bit sync header (10) before each 16-bit result. When DCO+ is ungrounded, it enters echoed clock mode and replicates the CLK+/CLK− input signal, allowing the host to latch data on the rising edge of DCO+. This dual-mode capability makes the AD7626BCPZ compatible with both FPGA and ASIC interfaces requiring deterministic timing alignment.

Can the AD7626BCPZ operate with a single 2.5 V supply?

No, the AD7626BCPZ requires three separate supply rails: VDD1 (4.75 V to 5.25 V analog), VDD2 (2.37 V to 2.63 V analog/digital), and VIO (2.37 V to 2.63 V I/O interface). These are not interchangeable - VDD1 powers the SAR core and reference buffer, VDD2 powers internal logic and clock generation, and VIO sets LVDS output levels. Operating the AD7626BCPZ with only a 2.5 V supply would violate absolute maximum ratings and prevent functional operation. The AD7626BCPZ datasheet specifies distinct current draw per rail (e.g., 11.2 mA typical on VDD1 at 10 MSPS).

How is the input common-mode voltage handled on the AD7626BCPZ?

The AD7626BCPZ generates its own input common-mode voltage at the VCM pin, which outputs exactly REF/2 (typically 2.048 V when REF = 4.096 V). This voltage is buffered and has low output impedance (5 kΩ), enabling direct connection to the common-mode input of differential drivers or fully differential amplifiers. The specified common-mode input range is VREF/2 ±50 mV, and the AD7626BCPZ achieves 68 dB CMRR at 1 MHz - critical for rejecting noise in high-density mixed-signal layouts. The VCM pin eliminates the need for external common-mode bias networks, simplifying front-end design for the AD7626BCPZ.