Analog Devices Inc. AD7667ACPZRL

Overview

AD7667ACPZRL from Analog Devices is a 16-bit, 1 MSPS charge redistribution SAR analog-to-digital converter with integrated 2.5 V reference, unipolar 0 V to 2.5 V input range, and dual serial/parallel interface. It operates from a single 5 V supply and delivers ±2.0 LSB INL, 88 dB S/(N+D) at 20 kHz, and no missing codes across temperature (–40°C to +85°C), targeting high-accuracy data acquisition in medical instruments and process control systems.

For engineers reviewing the AD7667ACPZRL datasheet, AD7667ACPZRL pinout, AD7667ACPZRL application, or AD7667ACPZRL equivalent, this page provides verified technical context, mode-specific throughput timing (Warp/Normal/Impulse), real-world interface behavior (SPI/QSPI/MICROWIRE-compatible serial, 16-bit parallel), and validated alternatives for precision unipolar ADC replacement in embedded signal chains.

Technical Context

The AD7667ACPZRL implements a factory-calibrated charge redistribution SAR architecture with internal error correction, eliminating pipeline delay and enabling immediate data availability post-conversion. Its three selectable conversion modes-Warp (1 µs cycle, 1 MSPS), Normal (1.25 µs, 800 kSPS), and Impulse (1.5 µs, 666 kSPS)-dynamically scale power consumption while maintaining full DC and AC specifications.

It integrates a 2.5 V reference with ±3 ppm/°C typical drift and supports external reference via REFBUFIN, with independent power domains (AVDD/DVDD/OVDD) and dedicated analog/digital/IO grounds (AGND/DGND/OGND). The dual-interface design allows seamless integration with 3 V or 5 V microcontrollers via configurable SER/PAR, OB/2C, BYTESWAP, and mode-select pins (WARP/IMPULSE).

Key Specifications

Pinout & Package

AD7667ACPZRL is housed in a 48-lead LFCSP package (7 mm × 7 mm, 0.8 mm height) with exposed paddle for thermal performance. Pin functions are validated per Analog Devices Rev. 0 datasheet Figure 4 and Table 6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit SAR ADC applications.

Compared with AD7671ASTZ and AD7666BCPZRL, AD7667ACPZRL uniquely combines internal 2.5 V reference, unipolar 0–2.5 V input, and 1 MSPS throughput in a single 5 V supply - reducing system-level component count, thermal load, and calibration effort for grounded-signal measurement applications.

Availability

AD7667ACPZRL is available at Aetrix Electronics and suitable for medical instrumentation, process control, and battery-powered systems requiring stable component supply, long-term lifecycle support, and guaranteed parametric compliance across –40°C to +85°C.

Supply support for AD7667ACPZRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The AD7667ACPZRL belongs to the PulSAR® family of precision SAR ADCs, designed specifically for applications demanding high resolution, high speed, and low power in space-constrained, thermally sensitive, or battery-operated equipment.

FAQ

What is the maximum sampling rate of the AD7667ACPZRL and under what conditions is it achieved?

The AD7667ACPZRL achieves a maximum sampling rate of 1 MSPS in Warp mode, which requires the WARP pin to be HIGH and IMPULSE pin LOW. This mode mandates a minimum conversion rate to guarantee full specified accuracy, and the complete conversion cycle time is 1 µs. At 1 MSPS, power dissipation is 133 mW typical with the internal reference enabled, and the device maintains ±2.0 LSB INL and 88 dB S/(N+D) performance across –40°C to +85°C.

Does the AD7667ACPZRL require an external reference, or does it include an internal one?

The AD7667ACPZRL includes a factory-trimmed 2.5 V internal reference with ±3 ppm/°C typical temperature drift and ±15 ppm/°C maximum drift over –40°C to +85°C. The PDREF pin controls reference activation: when PDREF is LOW, the internal reference is enabled and drives the REF pin; when HIGH, the internal reference is disabled and an external reference must be applied to REFBUFIN. This dual-mode capability eliminates external reference components for most unipolar applications while retaining flexibility for precision metrology.

How does the AD7667ACPZRL handle power management in low-duty-cycle applications?

The AD7667ACPZRL supports three power-optimized modes: Warp (1 MSPS), Normal (800 kSPS), and Impulse (666 kSPS), where power scales linearly with throughput. In Impulse mode, power drops to 130 µW at 1 kSPS without reference, and the PD pin allows full shutdown between conversions. Combined with independent PDREF and PDBUF controls, the AD7667ACPZRL enables microamp-level average current in battery-powered wake-on-event systems - critical for multi-year IoT sensor node operation.

Can the AD7667ACPZRL interface directly with 3 V microcontrollers, and how is level compatibility ensured?

Yes, the AD7667ACPZRL supports direct interfacing with 3 V microcontrollers via its OVDD pin, which accepts 2.7 V to 5.25 V and powers the IO interface domain. When OVDD = 3 V, all digital outputs (D[0:15], SDOUT, SYNC, etc.) meet 3 V logic thresholds (VOH ≥ 2.4 V, VOL ≤ 0.4 V), and inputs accept 3 V–compatible levels (VIH ≥ 2.0 V). The SER/PAR pin selects between parallel and serial modes, and OB/2C and BYTESWAP configure data format - enabling plug-and-play integration without external level shifters.

What are the key layout considerations for achieving specified AC performance with the AD7667ACPZRL?

To achieve the AD7667ACPZRL's specified 88 dB S/(N+D) and –96 dB THD, separate AGND and DGND planes must be joined at a single point near the device, with dedicated AVDD and DVDD decoupling (10 µF tantalum + 100 nF ceramic per supply). The analog input path (IN, INGND) must be routed away from digital traces, and the REF pin requires a 10 µF capacitor to REFGND. The exposed paddle must be soldered to a solid thermal pad connected to AGND - failure to follow these practices degrades SNR by >10 dB and increases harmonic distortion.