Analog Devices Inc. AD7679ACPZ

Overview

AD7679ACPZ from Analog Devices is an 18-bit, 570 kSPS, fully differential SAR analog-to-digital converter operating on a single 5 V supply. It features ±2.5 LSB INL, 103 dB dynamic range (VREF = 5 V), and dual parallel/serial interface support. It serves high-accuracy data acquisition in medical CT scanners and geophone sensor systems.

For engineers reviewing the AD7679ACPZ datasheet, AD7679ACPZ pinout, AD7679ACPZ application, or AD7679ACPZ equivalent, this page delivers verified specifications, package mapping, functional interface modes, real-world use-value per application, and two confirmed alternative ADCs for design flexibility under demanding SNR and linearity constraints.

Technical Context

The AD7679ACPZ employs charge redistribution SAR architecture with no pipeline delay, enabling immediate result availability after conversion. Its internal reference buffer supports 4.096 V output when 2.5 V is applied to REFBUFIN, and it accepts true differential inputs up to ±VREF (max 5 V).

It supports four configurable digital interface modes via MODE0/MODE1 pins: 18-bit parallel, 16-bit parallel (high/low word), 8-bit byte-aligned, and SPI/QSPI/MICROWIRE-compatible serial. Power management includes PDBUF control for reference buffer enable/disable and PD input for low-power shutdown.

Key Specifications

Pinout & Package

AD7679ACPZ is housed in a 48-lead LFCSP (Lead Frame Chip Scale Package) with exposed pad internally connected to AGND. The package supports thermal performance θJA = 26°C/W and requires soldering the EPAD to system analog ground for mechanical reliability.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-resolution SAR ADC applications.

Compared with AD7678ACPZ and AD7665ASTZ, the AD7679ACPZ uniquely delivers 18-bit resolution at 570 kSPS with integrated reference buffering and multimode serial/parallel flexibility - making it the only option among the three that satisfies simultaneous requirements for medical-grade linearity, CT scanner timing, and FPGA-hosted daisy-chained acquisition.

Availability

AD7679ACPZ is available at Aetrix Electronics and suitable for CT scanners, geophysical sensor arrays, and high-speed instrumentation requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for FDA-regulated or ISO 9001-certified production.

Supply support for AD7679ACPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with R&D and manufacturing infrastructure spanning North America, Europe, and Asia.

The AD7679ACPZ belongs to Analog Devices' PulSAR® family of precision SAR ADCs, engineered specifically for applications demanding high resolution, low latency, and exceptional DC/AC accuracy - including medical imaging, seismic monitoring, and automated test equipment.

FAQ

What is the maximum supported reference voltage for AD7679ACPZ?

The AD7679ACPZ accepts an external reference voltage up to AVDD + 0.1 V (5.35 V max at AVDD = 5.25 V). When using the internal reference buffer, applying 2.5 V to REFBUFIN yields a buffered 4.096 V output on REF, with tolerance of ±40 mV over temperature. This 4.096 V reference enables precise 18-bit scaling with 31.25 µV/LSB resolution.

Does AD7679ACPZ support true differential input operation?

Yes, AD7679ACPZ supports true differential input operation across IN+ and IN– pins with a full-scale range of ±VREF (up to ±5 V). Unlike pseudo-differential or single-ended ADCs, it performs simultaneous sampling of both inputs with matched front-end paths, delivering 68 dB CMRR at 100 kHz and eliminating offset drift caused by common-mode variations - critical for geophone and hydrophone sensor interfaces.

How does the PDBUF pin affect AD7679ACPZ performance?

The PDBUF pin controls the internal reference buffer: logic LOW enables the buffer (outputting ~4.096 V on REF when REFBUFIN = 2.5 V); logic HIGH disables it, allowing direct external reference connection. With PDBUF enabled, the AD7679ACPZ achieves ±0.5 ppm/°C gain drift and eliminates external op-amp requirements; with PDBUF disabled, reference accuracy depends entirely on external source stability and PCB layout.

Can AD7679ACPZ operate with a 3 V digital interface while using 5 V analog supply?

Yes, AD7679ACPZ supports mixed-voltage operation: AVDD and DVDD are independently rated for 4.75–5.25 V, while OVDD (digital I/O supply) operates from 2.7 V to 5.25 V. Setting OVDD = 3.3 V enables direct interfacing with 3 V FPGA or microcontroller I/O banks without level shifters, while maintaining full 5 V analog performance - verified in Table 2 and Figure 39–42 timing diagrams.

What is the purpose of the RDERROR pin on AD7679ACPZ?

The RDERROR pin functions exclusively in serial interface mode (MODE = 3) with EXT/INT = HIGH (external clock mode). It asserts a pulse when a serial read sequence is initiated but not completed before the next conversion finishes - indicating data loss due to insufficient host read timing. This flag enables firmware-level error recovery in daisy-chained multi-ADC systems where SDIN/SDOUT sharing increases read latency risk.