Analog Devices Inc. AD7688BRM

Overview

AD7688BRM from Analog Devices is a 16-bit, charge redistribution successive approximation ADC with true differential analog inputs, ±VREF input range, no pipeline delay, and 500 kSPS throughput. It operates from a single 5 V supply with 1.8 V–5 V logic interface (VIO), delivers ±1.5 LSB max INL and 95.5 dB SNR at 20 kHz, and targets high-precision data acquisition in battery-powered instrumentation.

For engineers reviewing the AD7688BRM datasheet, AD7688BRM pinout, AD7688BRM application, or AD7688BRM equivalent, this page provides verified specifications, validated pin functions, confirmed package mapping to 10-lead MSOP and LFCSP, real-world timing behavior (e.g., 0.5–1.6 µs conversion time), and two rigorously cross-checked alternative parts for design continuity.

Technical Context

The AD7688BRM implements a charge redistribution DAC architecture with dual 16-bit binary-weighted capacitor arrays, enabling precise differential sampling without latency. Its on-chip track-and-hold acquires voltage difference between IN+ and IN− on the CNV rising edge, with aperture delay of 2.5 ns and transient response of 400 ns after full-scale step.

It features a proprietary SPI-compatible serial interface supporting CS mode (3-/4-wire) and chain mode with daisy-chain capability and BUSY indicator. Power scales linearly with throughput: 3.75 µW at 100 SPS, 3.75 mW at 100 kSPS, and 21.5 mW at 500 kSPS - enabled by 1 nA standby current and internal conversion clock.

Key Specifications

Pinout & Package

The AD7688BRM is available in two RoHS-compliant packages: 10-lead MSOP (3 mm × 3 mm, 0.5 mm pitch) and 10-lead LFCSP (3 mm × 3 mm, exposed paddle). Both packages share identical pin numbering and function mapping per Analog Devices Rev. B datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit SAR ADC applications.

Compared with AD7688BRM, AD7687BRMZ offers identical form factor and precision at reduced speed and cost, while ADS8860IDRCT trades pin compatibility and integrated features for higher speed and lower supply voltage - requiring redesign of reference, power, and interface logic.

Availability

AD7688BRM is available at Aetrix Electronics and suitable for battery-powered equipment, medical instruments, process controls, and portable test equipment requiring stable component supply across long production lifecycles.

Supply support for AD7688BRM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD7688BRM belongs to the PulSAR™ family of precision SAR ADCs designed for high-speed, low-power, and high-accuracy data acquisition in space-constrained, battery-sensitive applications from −40°C to +85°C.

FAQ

What is the maximum recommended source impedance for driving the AD7688BRM analog inputs?

The AD7688BRM analog inputs exhibit optimal THD performance with source impedances ≤ 50 Ω, especially at higher input frequencies. At 100 kHz, THD degrades from −118 dB to −90 dB when source resistance increases from 33 Ω to 250 Ω. For best results, use low-output-impedance drivers or add RC filtering (e.g., 33 Ω + 2.7 nF) as shown in Figure 26 of the AD7688BRM datasheet. The AD7688BRM's internal RIN/CIN network forms a 1-pole filter that helps mitigate aliasing but cannot fully compensate for high-Z sources.

Does the AD7688BRM require an external reference voltage, and what are the constraints?

Yes, the AD7688BRM requires an external reference applied to the REF pin, which must be between 0.5 V and VDD (4.5 V–5.5 V). The reference load current is 100 µA at 500 kSPS, so the reference source must maintain regulation under this dynamic load. The AD7688BRM does not include an internal reference; using VDD as REF is permitted but limits input range to ±VDD. For highest accuracy, a low-noise, low-drift external reference (e.g., ADR4550) is recommended. The AD7688BRM datasheet specifies that gain error and SNR vary with REF voltage, as shown in Figures 13 and 16.

Can the AD7688BRM operate with a 3.3 V digital interface while using a 5 V analog supply?

Yes, the AD7688BRM supports independent analog and digital supplies: VDD = 5 V powers the ADC core, while VIO = 3.3 V sets logic thresholds for SDI, SCK, SDO, and CNV. This is explicitly supported per Table 3 (VIO range: 1.8 V to VDD + 0.3 V) and Figure 4 timing diagrams. The AD7688BRM's SPI-compatible interface remains fully functional with 3.3 V logic levels, eliminating need for level shifters. Ensure VIO decoupling is local and low-inductance to maintain signal integrity.

What is the significance of the "no pipeline delay" specification for the AD7688BRM?

"No pipeline delay" means the AD7688BRM is a true successive approximation register (SAR) ADC - not a pipelined or sigma-delta device - so its conversion result is available immediately after the conversion cycle completes, with zero cycles of latency. This enables deterministic timing in real-time control loops and multiplexed channel systems where sample-to-result delay must be fixed and minimal (e.g., 0.5–1.6 µs tCONV). Unlike pipelined ADCs, the AD7688BRM does not require flushing or synchronization overhead, simplifying firmware and guaranteeing that each CNV edge produces one valid output word.

How does the AD7688BRM handle daisy-chaining multiple ADCs, and what is the role of the SDI pin?

The AD7688BRM supports daisy-chaining via its SDI pin: when SDI is low during the CNV rising edge, the part enters Chain Mode. In this mode, SDI acts as a data-in port - the conversion result from the previous ADC in the chain is fed into SDI and appears on SDO after 16 SCK cycles. This allows multiple AD7688BRM units to share a single SDO line and one SCK/CNV pair, reducing PCB routing complexity. The AD7688BRM datasheet confirms this behavior in Pin Function Descriptions (Table 7) and Digital Interface sections (Pages 16–22), and it is distinct from CS Mode where SDI is used only for interface selection.