Analog Devices Inc. AD7712ANZ

Overview

AD7712ANZ from Analog Devices is a 24-bit sigma-delta analog-to-digital converter (ADC) designed for precision low-frequency signal conditioning in industrial measurement systems. It features dual analog input channels (AIN1 differential, AIN2 single-ended), programmable gain (1–128), on-chip 2.5 V reference, and digital filtering with configurable notch frequencies up to 1 kHz. It delivers ±0.0015% integral nonlinearity and supports single- or dual-supply operation (AVDD = 5–10 V, VSS = 0 or –5 V).

For engineers reviewing the AD7712ANZ datasheet, AD7712ANZ pinout, AD7712ANZ application, or AD7712ANZ equivalent, this page provides verified technical context, real-world use cases, calibrated performance metrics, package-specific layout guidance, and validated alternative options for smart transmitter, process control, and portable instrumentation designs.

Technical Context

The AD7712ANZ employs a charge-balancing sigma-delta architecture with an analog modulator followed by an on-chip digital filter whose first notch frequency is software-programmable via the control register - enabling precise rejection of 50 Hz/60 Hz interference. Its front end integrates a programmable-gain amplifier (PGA) for AIN1 and a resistor-based attenuator for AIN2, supporting simultaneous high- and low-level signal acquisition.

It implements three calibration modes (self-, system-, and background), allows read/write access to internal calibration registers, and supports bidirectional serial communication (TFS/RFS/SCLK/SDATA) in both self-clocking and external-clocking modes. The device achieves true 24-bit no-missing-codes resolution at filter notches ≤60 Hz and maintains 22-bit resolution at 100 Hz notch.

Key Specifications

Pinout & Package

AD7712ANZ is housed in a 24-lead, 0.3-inch wide plastic DIP (PDIP) package (N-24 suffix), compatible with through-hole PCB assembly and socket-based evaluation setups.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-precision sigma-delta ADC applications.

Compared with AD7712ANZ, AD7714BN offers more input channels but sacrifices the integrated reference and AIN2 high-level path, while ADS1258IPWR trades programmable notch filtering and transducer diagnostics for higher throughput and lower quiescent power - making each suitable for distinct subsystem roles within industrial measurement architectures.

Availability

AD7712ANZ is available at Aetrix Electronics and suitable for process control systems, smart transmitter designs, and portable industrial instruments requiring stable component supply, long-term lifecycle support, and traceable sourcing for safety-critical deployments.

Supply support for AD7712ANZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The AD7712ANZ belongs to Analog Devices' precision sigma-delta ADC product line, engineered specifically for low-frequency, high-resolution measurement front ends in harsh industrial environments where accuracy, noise immunity, and calibration integrity are paramount.

FAQ

What is the maximum sample rate of the AD7712ANZ at 24-bit resolution?

The AD7712ANZ achieves true 24-bit no-missing-codes resolution only at filter notch frequencies ≤60 Hz, corresponding to a maximum output data rate of approximately 100 SPS. At higher notch settings (e.g., 100 Hz), resolution degrades to 22 bits, enabling up to ~170 SPS. The exact rate depends on MCLK IN frequency (10 MHz nominal) and filter configuration - see Table III in the datasheet for full timing details. AD7712ANZ does not support oversampling beyond its fixed digital filter architecture.

Can the AD7712ANZ operate from a single 5 V supply?

Yes, the AD7712ANZ supports single-supply operation: tie VSS to AGND, set AVDD = +5 V, and configure inputs accordingly. In this mode, AIN1(±) must remain > –30 mV relative to VSS, and unipolar AIN1 input range becomes 0 V to VREF/GAIN. The internal 2.5 V reference (REF OUT) remains functional, and all digital I/O operates at DVDD = +5 V. This configuration is widely used in 5 V microcontroller-based smart transmitter designs.

Does the AD7712ANZ support simultaneous sampling of both analog inputs?

No, the AD7712ANZ does not support simultaneous sampling. It uses a single sigma-delta modulator shared between AIN1 and AIN2; channel selection is performed via internal multiplexing under software control. While fast switching (<10 µs) allows near-simultaneous acquisition, true concurrent sampling is not implemented. For synchronized multi-channel capture, external sample-and-hold or multiple AD7712ANZ devices with SYNC pin coordination are required.

How is transducer burnout detection implemented on the AD7712ANZ?

The AD7712ANZ provides a 4.5 µA nominal current source connected to the AIN1(+) pin, controllable via the control register's BURN bit. When enabled, this current flows through the external transducer; open-circuit conditions cause AIN1(+) to rise toward AVDD, detectable as an out-of-range reading. The feature is specified with ±10% initial tolerance and 0.1%/°C drift, and requires no external components - a key enabler for self-diagnostic smart sensors using AD7712ANZ.

What are the absolute maximum ratings for AVDD and VSS on the AD7712ANZ?

The AD7712ANZ has an absolute maximum AVDD-to-VSS rating of +12 V. Per the datasheet, AVDD may range from +5 V to +10 V (±5% for specified performance), and VSS may be 0 V (for single supply) or –5 V (for dual supply). Exceeding AVDD = +10.5 V or VSS = –6 V violates absolute maximum ratings and risks permanent damage. Operation at AVDD = +10 V with VSS = –5 V is permitted, provided AVDD – VSS ≤ +10.5 V and all other supply constraints (e.g., DVDD ≤ AVDD + 0.3 V) are met.